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| [ak4343] ms0478-j-02 2010/11 - 1 - ? a ak4343 x???????z3???s?| 1.2w z?we???? o `ha| dac pb{?????3??s?q pll ? o `os?z pmp( ?????y???? ) ? 3 ?; mw3aq0?t?????? ?\qud pb{?- ?x ?w 32pin qfn ?>;z hr3aq
z`o? ? u? g ?t_n`?b{ ? ? 1. 6 \ ; ? ?????????3???? (tc=50/15 s, fs=32khz, 44.1khz, 48khz) ? ?? ? 1????? ? ??????? o (+12db ? 115.0db, 0.5db step, mute) ? digital alc (automatic level control) s? o (+36db ? 54db, 0.375db step, mute) ? a| es? ? a|??? z? ? programmable eq - ? q : s/(n+d): 88db, s/n: 92db ? t??3??? o - btl output - z? : 30mw@32 (avdd=3.3v) ? a|??????? o - hp-amp ? q : s/(n+d): 70db@7.5mw, s/n: 90db - z? : 70mw@16 (hvdd=5v), 62mw@16 (hvdd=3.3v) - ?o on/off ????????? ? t??e??? o - spk-amp ? q : s/(n+d): 50db@240mw, s/n: 90db - btl ? - y ?e? 0 - z? : 1.2w@8 (hvdd=5v), 400mw@8 (hvdd=3.3v) 3.0vrms@50 (hvdd=5v) ? ?????3?? : - 3 a| ?? - ????? o (+32db/+26db/+20db or 0db) 2. ??y??; 3. ???? : (1) pll t?? ? * t : : 11.2896mhz,12mhz ,12.288mhz,13.5m hz,24mhz,27mhz (mcki pin) 1fs (lrck pin) 32fs or 64fs (bick pin) (2) ? ????t?? ? * t : : 256fs, 512fs or 1024fs (mcki pin) 4. ???? z? * t : : 32fs/64fs/128fs/256fs 5. ???? * t : : ? pll slave mode (lrck pin): 7.35khz 48khz ? pll slave mode (bick pin): 7.35khz 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz stereo dac with hp/rcv/spk- a mp ak4343 [ak4343] ms0478-j-02 2010/11 - 2 - ? ext master/slave mode: 7.35khz 48khz (256fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 6. 3??? p ????? : 3 3??? , i 2 c (ver 1.0, 400khz ? t?? ) 7. ???t?? 8. |???|????????? : msb first, 2?s complement ? 16bit 2g? , 16bit ?g? , 16-24bit i 2 s, dsp mode 9. ta = ? 30 85 c (ak4343en) ? 40 85 c (AK4343VN) 10. ?o ?y : ? avdd, dvdd: 2.6 3.6v (typ. 3.3v) ? hvdd: 2.6 5.25v (typ. 3.3v/5.0v) 11. ?-? : 32pin qfn (5mm x 5mm, 0.5mm pitch) 12. ak4642en qe? / ??? ?? $ gain-amp pmmicl pmmicr audio i/f d/a datt smute pmdac pmhpl pmhpr line in stereo line out or mono receiver headphone pmspk speaker bass boost pll pmpll control register lin1 rin1 lin2 rin2 hpl hpr mutet spp spn hvdd hvss avdd a vss vcom dvdd csn pdn cclk cdti bick lrck sdti mcko mcki vcoc pmlo lout/rcp rout/rcn alc dvss stereo separation hpf i2c lin3/min rin3/vcoc pmainr2 pmainl2 pmainr3 pmainl3 figure 1. ?? $ [ak4343] ms0478-j-02 2010/11 - 3 - |??????? ak4343en ? 30 +85 c 32pin qfn (0.5mm pitch) AK4343VN ? 40 +85 c 32pin qfn (0.5mm pitch) akd4343 ak4343 ; a??? e? ? mu te t rout / rcn lout / rcp min / lin3 rin2 / in2 ? lin2 / in2+ lin1 / in1 ? rin1 / in1+ hpl hp r hvss hvdd spp spn mcko mcki test1 vcom avss avdd vcoc / rin3 i2c pdn csn / cad0 dvss dvdd bick lrck test2 sdti cdti / sd a cclk / scl ak4343 top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 ak4642en qw?? q 1. ; ; ak4642en ak4343 spk-amp z? 400mw@3.3v 1.2w@5v hp-amp z? 62mw@3.3v 70mw@5v receiver-amp no yes ?????3?? 1 mono 3 stereo adc yes no alc ?? *8 128/fs 1024/fs 128/fs 16384/fs alc ?????? s 4 4 , 8 , 16 dsp format no yes ext master mode no yes dac group delay 22/fs 25/fs [ak4343] ms0478-j-02 2010/11 - 4 - 2. e? pin# ak4642en ak4343 1 mpwr test1 5 vcoc vcoc/rin3 12 sdto test2 26 rout rout/rcn 27 lout lout/rcp 28 min min/lin3 3. ? addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin pmspk pmlo pmdac 0 pmadl 01h power management 2 0 hpmt n pmhpl pmhpr m/s 0 mcko pmpll 02h signal select 1 sppsn mins dacs dacl 0 pmmp 0 mgain0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 minl 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control avl 7 avl6 avl5 avl4 avl 3 avl2 avl1 avl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 loop smute dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 avolc hpm minh dach 10h power management 3 inr1 inl1 hpg mdif2 mdif1 inr0 inl0 pmadr 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h power management 4 0 0 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl 21h mode control 5 0 0 micr3 micl3 0 0 ain3 rcv 22h lineout mixing select 0 0 0 0 rinr3 linl3 rinr2 linl2 23h hp mixing select 0 0 0 0 rinh3 linh3 rinh2 linh2 24h spk mixing select 0 0 0 0 rins3 lins3 rins2 lins2 ak4343 p ?c^?h??? ak4343 p_ ?^?h??? [ak4343] ms0478-j-02 2010/11 - 5 - e??; no. pin name i/o function 1 test1 - a? 1 e? |??t`o<^m{ 2 vcom o t? ?y z?e? , 0.45 x avdd dac z?w?? ?ypb{ 3 avss - ???????e? 4 avdd - ??? ?oe? vcoc o pll w??????; z?e? (ain3 bit = ?0? : pll ?;d ) avss qwt ?q????3??? ? `o<^m{ 5 rin3 i rch ??? ?? 3 e? (ain3 bit = ?1? : pll ?; ?d ) 6 i2c i ????t?? ? re? ?h?: i 2 c , ?l?: 3 3??? 7 pdn i ????t??e? ?h?: ???? ?l?: ????z???z?????w s8= csn i ????e? (i2c pin = ?l? : 3 3???t?? ) 8 cad0 i ???? 0 e? (i2c pin = ?h? : i 2 c t?? ) cclk i ??????? ??e? (i2c pin = ?l? : 3 3???t?? ) 9 scl i ??????? ??e? (i2c pin = ?h? : i 2 c t?? ) cdti i ??????? ??e? (i2c pin = ?l? : 3 3???t?? ) 10 sda i/o ??????? ? z?e? (i2c pin = ?h? : i 2 c t?? ) 11 sdti i |???|3?????? ??e? 12 test2 - a? 2 e? |??t`o<^m{ 13 lrck i/o ? z???????e? 14 bick i/o |???|3??????e? 15 dvdd - ???? ?oe? 16 dvss - ????????e? 17 mcki i ? ????? ??e? 18 mcko o ???? z?e? 19 spn o e??? s 8 z?e? 20 spp o e??? ? s 8 z?e? 21 hvdd - ??????? & e??? ?oe? 22 hvss - ??????? & e???????e? 23 hpr o rch ??????? z?e? 24 hpl o lch ??????? z?e? 25 mutet o ??? :????e? hvss e?qwt : ? ;???? ? `?b{ rout o rch ??? z?e? (rcv bit = ?0? : 3?????a| z? ) 26 rcn o 3??? s 8 z?e? (rcv bit = ?1? : btl z? ) lout o lch ??? z?e? (rcv bit = ?0? : 3?????a| z? ) 27 rcp o 3??? ? s 8 z?e? (rcv bit = ?1? : btl z? ) min i t????? ??e? (ain3 bit = ?0? : pll ?;d ) 28 lin3 i lch ??? ?? 3 e? (ain3 bit = ?1? : pll ?; ?d ) rin2 i rch ??? ?? 2 e? (mdif2 bit = ?0? : 3????? ?? ) 29 in2 ? i rch s 8 ?? 2 e? (mdif2 bit = ?1 : ) ? ?? ?) lin2 i lch ??? ?? 2 e? (mdif2 bit = ?0? : 3????? ?? ) 30 in2+ i rch ? s 8 ?? 2 e? (mdif2 bit = ?1? : ) ? ?? ) lin1 i lch ??? ?? 1 e? (mdif1 bit = ?0? : 3????? ?? ) 31 in1 ? i lch s 8 ?? 1 e? (mdif1 bit = ?1? : ) ? ?? ) rin1 i rch ??? ?? 1 e? (mdif1 bit = ?0? : 3????? ?? ) 32 in1+ i lch ? s 8 ?? 1 e? (mdif1 bit = ?1? : ) ? ?? ) note 1. ??? ??e? (min/lin3, lin1, rin1, lin2, rin2, rin3) ??wb?ow ??e?x??a?? ?t`oxmz?d?{ note 2. i2c pin tx avdd ?`xx avss ? ??`o<^m{ [ak4343] ms0478-j-02 2010/11 - 6 - ?;`sme?w rgtmmo ?;`sm ? z?e?x<gw ? ??mz & ~t rg`o<^m{ e? ? analog vcoc/rin3, spn, spp, hpr, hpl, mutet, rout/rcn, lout/rcp, min/lin3, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ |?? mcko |?? digital mcki dvss t ? ? 07 g (avss=dvss=hvss=0v; note 3 ) parameter symbol min max units power supplies: analog avdd ? 0.3 6.0 v digital dvdd ? 0.3 6.0 v headphone-amp / speaker-amp hvdd ? 0.3 6.0 v |avss ? dvss| ( note 4 ) gnd1 - 0.3 v |avss ? hvss| ( note 4 ) gnd2 - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 5 ) vina ? 0.3 avdd+0.3 v digital input voltage ( note 6 ) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ak4343en ta ? 30 85 c AK4343VN ta ? 40 85 c storage temperature tstg ? 65 150 c maximum power dissipation ta=85 c ( note 8 ) pd1 - 750 mw ( note 7 ) ta=70 c ( note 9 ) pd2 - 1000 mw note 3. ?yxb?o????e?t 0b? ?pb{ note 4. avss q dvss, hvss x ?a???????t ? `o<^m{ note 5. i2c, min/lin3, rin3, rin2/in2 ? , lin2/in2+, lin1/in1 ? , rin1/in1+ pins note 6. pdn, csn/cad0, cclk/scl, cd ti/sda, sdti, lrck, bick, mcki pins sda, scl pins w??? ?w ? ?x (dvdd+0.3)v ?<t`o<^m{ note 7. ?-?j?we z??????t ? `z? ^?????, xw s 100% ? w ? pb{?-?j?we z??|??t`h ?x pd1=400mw(max: e????; ? d ), pd2=550mw(max: hvdd=2.6 3.6v toe????;d ) pb{\w ?? ?x ak4343 w o ? ? pz? ? ? ^??e?s?|?????pw ? ? x???d?{ note 8. hvdd=2.6 3.6v toe?????;b?\qupv?b{ note 9. hvdd=2.6 5.25v toe?????;b?\qupv?b{ ?? : \w ?? qh ep?;`h ?z??? ub?\quk??b{?hz w ?^x- a ^??d?{ [ak4343] ms0478-j-02 2010/11 - 7 - * ? ?^ e (avss=dvss=hvss=0v; note 3 ) parameter symbol min typ max units power supplies analog avdd 2.6 3.3 3.6 v ( note 10 ) digital dvdd 2.6 3.3 3.6 v hp / spk-amp hvdd 2.6 3.3 / 5.0 5.25 v difference avdd ? dvdd ? 0.3 0 +0.3 v note 3. ?yxb?o????e?t 0b? ?pb{ note 10. avdd, dvdd, hvdd w ?oqj [3?-????b? ?axk??d?{ avdd, hvdd iz off `h ?z dvdd w??? ?vu ?cb?d quk??b{ ?hz dvdd ? off b? ?x avdd, hvdd ? off `oxi^m{ ?? : ????3??tgl^?om? e??w]?;t`oxz ptpx y ?mtv?bwp g ] ??<^m{ ??? ? q (ta=25 c; avdd=dvdd=hvdd=3.3v; avss=dvss=hvss= 0v; fs=44.1khz, bick=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units gain amplifier: lin1/rin1/lin2/rin2 pins & lin3/rin3 pins (ain3 bit = ?1?); mdif1=mdif2 bits = ?0? (single-ended inputs) mgain1-0 bits = ?00? 40 60 80 k input resistance mgain1-0 bits = ?01?, ?10?or ?11? 20 30 40 k mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - +20 - db mgain1-0 bits = ?10? - +26 - db gain mgain1-0 bits = ?11? - +32 - db gain amplifier: in1+/in1 ? /in2+/in2 ? pins; mdif1 = mdif2 bits = ?1? (full-differential input) input voltage ( note 11) mgain1-0 bits = ?01? - - 0.228 vpp mgain1-0 bits = ?10? - - 0.114 vpp mgain1-0 bits = ?11? - - 0.057 vpp note 11. ? ??e?q?? ??e?w) pb{ ac ???????? ??e?t3?? ?t ? `o<^m{ mgain1-0 bits = ?00? wqv) ? ??x?;e-pb{ in1+, in1 ? , in2+, in2 ? pin w7 g ?? ?yxf?g? avdd t z?`?b{ vin = |(in+) ? (in ? )| = 0.069 x avdd (max)@mgain1-0 bits = ?01?, 0.035 x avdd (max)@mgain1-0 bits = ?10?, 0.017 x avdd (max)@mgain1-0 bits = ?11?. \w ?y?yq? ??u ??^?h ?z amp w ?^x- apv?d?{ [ak4343] ms0478-j-02 2010/11 - 8 - parameter min typ max units dac characteristics: resolution - - 16 bits stereo line output characteristics: dac lout/rout pins, alc=off, avol=0db, dvol=0db, lovl bit = ?0?, rcv bit = ?0?, r l =10k ; unless otherwise specified. output voltage ( note 12 ) lovl bit = ?0? 1.78 1.98 2.18 vpp lovl bit = ?1? 2.25 2.50 2.75 vpp s/(n+d) ( ? 3dbfs) 78 88 - dbfs s/n (a-weighted) 82 92 - db interchannel isolation pmainl2/r2/l3/r3 bits = ?1? 80 100 - db pmainl2/r2/l3/r3 bits = ?0? - 100 - db interchannel gain mismatch - 0.1 0.5 db load resistance 10 - - k load capacitance - - 30 pf mono receiver output characteristics: dac rcp/rcn pins, alc=off, avol =0db, dvol=0db, lovl bit = ?0?, rcv bit = ?1?, r l =32 , btl; unless otherwise specified. output voltage ( note 13 ) lovl bit = ?0?, ? 6dbfs, r l =32 (po=15mw) 1.57 1.96 2.35 vpp lovl bit = ?0?, ? 3dbfs, r l =32 (po=30mw) - 2.77 - vpp lovl bit = ?1?, ? 8dbfs, r l =32 (po=15mw) 1.57 1.96 2.35 vpp lovl bit = ?1?, ? 5dbfs, r l =32 (po=30mw) - 2.77 - vpp s/(n+d) lovl bit = ?0?, ? 6dbfs, r l =32 (po=15mw) 40 60 - db lovl bit = ?0?, ? 3dbfs, r l =32 (po=30mw) - 60 - db s/n (a-weighted) 85 95 - dbfs load resistance 32 - - load capacitance - - 30 pf note 12. z? ?yx avdd t z?`?b{ vout = 0.6 x avdd (typ)@lovl bit = ?0?. note 13. z? ?yx avdd t z?`?b{ vout = 0.59 x avdd (typ)@lovl bit = ?0?, ? 6dbfs. [ak4343] ms0478-j-02 2010/11 - 9 - parameter min typ max units headphone-amp characteristics: dac hpl/hpr pins, alc=off, avol= 0db, dvol=0db; unless otherwise specified. output voltage ( note 14 ) hpg bit = ?0?, 0dbfs, hvdd=3.3v, r l =22.8 1.58 1.98 2.38 vpp hpg bit = ?1?, 0dbfs, hvdd=5v, r l =100 2.40 3.00 3.60 vpp hpg bit = ?1?, 0dbfs, hvdd=3.3v, r l =16 (po=62mw) - 1.0 - vrms hpg bit = ?1?, 0dbfs, hvdd=5v, r l =16 (po=70mw) - 1.06 - vrms s/(n+d) hpg bit = ?0?, ? 3dbfs, hvdd=3.3v, r l =22.8 60 70 - dbfs hpg bit = ?1?, ? 3dbfs, hvdd=5v, r l =100 - 80 - dbfs hpg bit = ?1?, 0dbfs, hvdd=3.3v, r l =16 (po=62mw) - 20 - dbfs hpg bit = ?1?, 0dbfs, hvdd=5v, r l =16 (po=70mw) - 70 - dbfs ( note 15 ) 80 90 - db s/n (a-weighted) ( note 16 ) - 90 - db interchannel isolation ( note 15 ), pmainl2/r2/l3/r3 bits = ?1? 65 75 - db ( note 15 ), pmainl2/r2/l3/r3 bits = ?0? - 75 - db ( note 16 ) - 80 - db ( note 15 ) - 0.1 0.8 db interchannel gain mismatch ( note 16 ) - 0.1 0.8 db load resistance 16 - - figure 2 w c1 - - 30 pf load capacitance figure 2 w c2 - - 300 pf note 14. z? ?yx avdd t z?`?b{ vout = 0.6 x avdd(typ)@hpg bit = ?0 ?, 0.91 x avdd(typ)@hpg bit = ?1?. note 15. hpg bit = ?0?, hvdd=3.3v, r l =22.8 . note 16. hpg bit = ?1?, hvdd=5v, r l =100 . hpl/hpr pin hp-amp 47 f c1 16 c2 6.8 0.22 f 10 measurement point figure 2. ??????? z?s? [ak4343] ms0478-j-02 2010/11 - 10 - parameter min typ max units speaker-amp characteristics: dac spp/spn pins, alc=off, avol=0db, dvol=0db, r l =8 , btl, hvdd=3.3v; unless otherwise specified. output voltage ( note 17 ) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 3.11 - vpp spkg1-0 bits = ?01?, ? 0.5dbfs (po=240mw) 3.13 3.92 4.71 vpp hvdd=5v, spkg1-0 bits = ?11?, 0dbfs (po=1w) - 2.83 - vrms line input ? spp/spn pins, hvdd=5v, spkg1-0 bits = ?11?, ? 1.5dbv input (po=1.2w) - 3.1 - vrms s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 60 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=240mw) 20 50 - db hvdd=5v, spkg1-0 bits = ?11?, 0dbfs (po=1w) - 30 - db line input ? spp/spn pins, hvdd=5v, spkg1-0 bits = ?11?, ? 1.5dbv input (po=1.2w) - 20 - db s/n (a-weighted) 80 90 - db load resistance 8 - - load capacitance - - 30 pf speaker-amp characteristics: dac spp/spn pins, alc=off, avol=0db, dvol=0db, c l =3 f, r series =10 x 2, btl, hvdd=5.0v; unle ss otherwise specified. output voltage spkg1-0 bits = ?10?, 0dbfs - 6.75 - vpp ( note 17 ) spkg1-0 bits = ?11?, 0dbfs 6.80 8.50 10.20 vpp s/(n+d) spkg1-0 bits = ?10?, 0dbfs - 60 - db ( note 18 ) spkg1-0 bits = ?11?, 0dbfs 40 50 - db s/n (a-weighted) 80 90 - db load impedance ( note 19 ) 50 - - load capacitance ( note 19 ) - - 3 f mono input: min pin (ain3 bit = ?0?; external input resistance=20k ) maximum input voltage ( note 20 ) - 1.98 - vpp gain ( note 21 ) min ? lout/rout lovl bit = ?0? ? 4.5 0 +4.5 db lovl bit = ?1? - +2 - db min ? hpl/hpr hpg bit = ?0? ? 24.5 ? 20 ? 15.5 db hpg bit = ?1? - ? 16.4 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? ? 0.07 +4.43 +8.93 db alc bit = ?0?, spkg1-0 bits = ?01? - +6.43 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.65 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?00? - +6.43 - db alc bit = ?1?, spkg1-0 bits = ?01? - +8.43 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.65 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.65 - db note 17. z? ?yx avdd t z?`?b{ full-differential w ?z vout = (spp) ? (spn) = 0.94 x avdd(typ)@spkg1-0 bits = ?00?, 1.19 x avdd(typ)@spkg1-0 bits = ?01?, 2.05 x avdd(typ)@spkg1-0 bits = ?10?, 2.58 x avdd(typ)@spkg1-0 bits = ?11? pb{ note 18. :x spp/spn pins pb{ note 19. figure 58 tsmoz load impedance x3??? ? (r series ) q 1khz tsz?y ?e?w??e?? ?w r??e???pb{ load capacitance xy ?e?w0? r pb{y ?e?? ?;b? ?z spp, spn pin tf?g? 10 ? w3??? ?? ? `o<^m{ note 20. 7 g ?? ?yx avdd q? ? ?? ? (rin) t z?`?b{ vin = 0.6 x avdd x rin / 20k (typ). note 21. ???x? ? ?? ?t s z?`?b{ [ak4343] ms0478-j-02 2010/11 - 11 - parameter min typ max units stereo input: lin2/rin2 pins; lin3/rin3 pins (ain3 bit = ?1?) maximum input voltage ( note 22 ) - 1.98 - vpp gain lin/rin ? lout/rout lovl bit = ?0? ? 4.5 0 +4.5 db lovl bit = ?1? - +2 - db lin/rin ? hpl/hpr hpg bit = ?0? ? 4.5 0 +4.5 db hpg bit = ?1? - +3.6 - db lin/rin ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? ? 6.09 ? 1.59 +2.91 db alc bit = ?0?, spkg1-0 bits = ?01? - +0.41 - db alc bit = ?0?, spkg1-0 bits = ?10? - +4.63 - db alc bit = ?0?, spkg1-0 bits = ?11? - +6.63 - db alc bit = ?1?, spkg1-0 bits = ?00? - +0.41 - db alc bit = ?1?, spkg1-0 bits = ?01? - +2.41 - db alc bit = ?1?, spkg1-0 bits = ?10? - +6.63 - db alc bit = ?1?, spkg1-0 bits = ?11? - +8.63 - db power supplies: power up (pdn pin = ?h?) all circuit power-up: avdd+dvdd ( note 23 ) - 12 18 ma hvdd: hp-amp normal operation no output ( note 24 ) - 5 8 ma hvdd: spk-amp normal operation no output ( note 25 ) - 11 30 ma power down (pdn pin = ?l?) ( note 26 ) avdd+dvdd+hvdd - 10 100 a note 22. 7 g ?? ?yx avdd t z?`?b{ vin = 0.6 x avdd (typ). note 23. pll master mode (mcki=12.288mhz) pz pmdac = pmlo = pmhpl = pmhpr = pmvcm = pmpll = mcko = pmmin = m/s = pmmicl = pmmicr bits = ?1? w ?pb{ avdd=9ma(typ), dvdd=3ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?) w ? : avdd=8ma(typ), dvdd=2ma(typ). note 24. pmdac = pmlo = pmhpl = pmhpr = pmvcm = pmpll = pmmin bits = ?1?, tm pmspk bit = ?0? w ?pb{ note 25. pmdac = pmlo = pmspk = pm vcm = pmpll = pmmin bits = ?1?, tm pmhpl = pmhpr bits = ?0? w ?pb{ note 26. ?ow???? ??e?? dvdd ?hx dvss t{ `hw ?pb{ [ak4343] ms0478-j-02 2010/11 - 12 - t?? w ? ? ?? e : ta=25 c; avdd=dvdd=hvdd=3.3v; avss=dvss=hvss=0v; fs =44.1khz, external slave mode, bick=64fs ; 1khz, 0dbfs input; headphone & speaker = no output power management bit 00h 01h 20h mode pmvcm pmmin pmspk pmlo pmdac pmhpl pmhpr pmmicl pmmicr pmainl2 pmainr2 pmainl3 pmainr3 avdd [ma] dvdd [ma] hvdd [ma] total power [mw] all power-down 0 0 00 0 0 0000000 0 0 0 0 dac ? lineout 1 0 01 1 0 0000000 5.4 1.8 0.2 24.4 dac ? hp 1 0 00 1 1 1000000 3.7 1.8 5 34.7 dac ? spk 1 0 10 1 0 0000000 3.7 1.8 11 54.5 lin2/rin2 ? hp 1 0 00 0 1 1001100 1.9 0 5 22.8 lin2/rin2 ? spk 1 0 10 0 0 0001100 1.9 0 11 42.6 min ? rcv 1 1 01 0 0 0000000 3.1 0 0.2 10.9 table 1. t?? w ? ? ?? (typ) ???? ? q (ta=25 c; avdd=dvdd=2.6 3.6v; hvdd=2.6 5.25v; fs=44.1khz; dem=off; fil1=fil3=eq=off) parameter symbol min typ max units dac digital filter (lpf): passband ( note 27 ) 0.1db pb 0 - 19.6 khz ? 0.7db - 20.0 - khz ? 6.0db - 22.05 - khz stopband sb 25.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 59 - - db group delay ( note 28 ) gd - 25 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db dac digital filter (hpf): frequency response ( note 27 ) ? 3.0db fr - 0.9 - hz ? 0.5db - 2.7 - hz ? 0.1db - 6.0 - hz boost filter: ( note 29 ) min 20hz fr - 5.76 - db 100hz - 2.92 - db 1khz - 0.02 - db mid 20hz fr - 10.80 - db 100hz - 6.84 - db 1khz - 0.13 - db max 20hz fr - 16.06 - db 100hz - 10.54 - db frequency response 1khz - 0.37 - db note 27. ? ? qw * t :x fs ( 3a?????? ) t z?`?b{ ?qyz pb=20.0khz(@ ? 0.7db) x 0.454 x fs pb{ tx 1khz ?, jt`?b{ note 28. ????????t?? ? ?pz 16 ??????u ???t??^?ot??? ? ??u z?^???pwpb{ pmadl=pmadr bits = ?0? wqv dac ?w group delay x 25/fs(typ) pb note 29. * t : ? qx??????t z?`?b{???w ? * t ??? ??`h ?z ??p? ??`?b{ [ak4343] ms0478-j-02 2010/11 - 13 - dc ? q (ta=25 c; avdd=dvdd=2.6 3.6v; hvdd=2.6 5.25v) parameter symbol min typ max units high-level input voltage vih 70%dvdd - - v low-level input voltage vil - - 30%dvdd v high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 a ????? ? q (ta=25 c; avdd=dvdd=2.6 3.6v; hvdd=2.6 5.25v; c l =20pf; unless otherwise specified) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns [ak4343] ms0478-j-02 2010/11 - 14 - parameter symbol min typ max units pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % [ak4343] ms0478-j-02 2010/11 - 15 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bick ? ? ( note 30 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bick ? ? ( note 31 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck ? ? to bick ? ? ( note 30 ) tlrb 0.4 x tbck - - ns lrck ? ? to bick ? ? ( note 31 ) tlrb 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 30 ) tblr 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 31 ) tblr 0.4 x tbck - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns audio interface timing (r ight/left justified & i 2 s) master mode bick ? ? to lrck edge ( note 32 ) tmblr ? 40 - 40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 32 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 32 ) tblr 50 - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 30. msbs, bckp bits = ?00? or ?11?. note 31. msbs, bckp bits = ?01? or ?10?. note 32. \wf ?x lrck w?q bick w ? ? u os?sm?otf `om?b{ [ak4343] ms0478-j-02 2010/11 - 16 - parameter symbol min typ max units control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 34 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 35 ) tpd 150 - - ns note 33. i 2 c-bus x nxp b.v. w ? apb{ note 34. ???x7 ? 300ns (scl wqj<u? ) w-?^?sz?ys??d?{ note 35. ak4343 x pdn pin = ?l? p???^??b{ [ak4343] ms0478-j-02 2010/11 - 17 - ????? t lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 figure 3. clock timing (pll/ext master mode) note 36. mcko is not available at ext master mode. lrck bick 50%dvdd dbck tdbf 50%dvdd tlrckh tbck bick 50%dvdd (bckp = "0") (bckp = "1") tsds sdti vil tsdh vih figure 4. audio interface timing (pll/ext master mode, dsp mode, msbs = ?0?) [ak4343] ms0478-j-02 2010/11 - 18 - lrck bick 50%dvdd dbck tdbf 50%dvdd tlrckh tbck bick 50%dvdd (bckp = "1") (bckp = "0") tsds sdti vil tsdh vih figure 5. audio interface timing (pll/ext master mode, dsp mode, msbs = ?1?) lrck 50%dvdd bick 50%dvdd tsds sdti vil tsdh vih tblr tbckl figure 6. audio interface timing (pll/ ext master mode, except dsp mode) [ak4343] ms0478-j-02 2010/11 - 19 - 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "0") (bckp = "1") figure 7. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?0?) 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "1") (bckp = "0") figure 8. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?1?) [ak4343] ms0478-j-02 2010/11 - 20 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 9. clock timing (pll slave mode; pll reference clock = mcki pin, except dsp mode) lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = ?0?) [ak4343] ms0478-j-02 2010/11 - 21 - lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 11. audio interface timing (pll slave mode, dsp mode, msbs = ?1?) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 12. clock timing (ext slave mode) [ak4343] ms0478-j-02 2010/11 - 22 - lrck vih vil tblr bick vih vil tlrb tsds sdti vil tsdh vih figure 13. audio interface timing (pll/ ext slave mode, except dsp mode) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 14. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 15. write data input timing [ak4343] ms0478-j-02 2010/11 - 23 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 16. i 2 c t??????? tpd pdn vil figure 17. power down & reset timing [ak4343] ms0478-j-02 2010/11 - 24 - ; ? 3a??? ? ?qw i/f t??x?<w 4 ?wmouk??b{ ( table 2 and table 3 ) mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 37 ) 1 1 see table 5 figure 18 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 5 figure 19 pll slave mode 2 (pll reference clock: lrck or bick pin) 1 0 see table 5 figure 20 figure 21 ext slave mode 0 0 x figure 22 ext master mode 0 1 x figure 23 note 37. pll master mode t ? b?a pz m/s bit = ?1?, pmpll b it = ?0?, mcko bit = ?1? wqv mcko pin t? y psm * t :w???u z?^??b{ table 2. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 ?l? pll master mode 1 ps1-0 bits p ? r pll3-0 bits p ? r output (bcko bit p ? r ) output (1fs) 0 ?l? pll slave mode (pll reference clock: mcki pin) 1 ps1-0 bits p ? r pll3-0 bits p ? r input ( 32fs) input (1fs) pll slave mode (pll reference clock: lrck or bick pin) 0 ?l? gnd input (pll3-0 bits p ? r ) input (1fs) ext slave mode 0 ?l? fs1-0 bits p ? r input ( 32fs) input (1fs) ext master mode 0 ?l? fs1-0 bits p ? r output (bcko bit p ? r ) output (1fs) table 3. clock pins state in clock mode ?t??q?t??w ~? 8q ?t??q?t??w ~? 8qx m/s bit p?m?b{ ?1? p?t??z ?0? p?t?? pb{ ak4343 x???? (pdn pin = ?l?) zt|????r ??x?t??pb{?? ??r ??z m/s bit ? ?1? t!?b?\qp?t??ts??b{ ?t??p?;b? ?z m/s bit t ?1? u {v????pz ak4343 w lrck, bick pin x??a?? ?w y 6pb{fwh?z ak4343 w lrck, bick pin t 100k sw???k?mx??? ?? ? ?? ?auk??b{ m/s bit mode 0 slave mode (default) 1 master mode table 4. select master/slave mode [ak4343] ms0478-j-02 2010/11 - 25 - pll t?? (ain3 bit = ?0?, pmpll bit = ?1?) pmpll bit = ?1? wz o w? ^ s??? pll x fs3-0 bits, pll3-0 bits p ? r`h???t ao ?^` ?b{ pll w??xz ?o d ??z pmpll bit ? ?0? ? ?1? t!?`z? `h???u ??^?h ?z?hx???? * t :u!?^?h ?z table 5 w ?pb{ ain3 bit = ?1? wqv pll x?;p v?d?{ 1) pll mode w ? vcoc pin w r,c mode pll3 bit pll2 bit pll1 bit pll0 bit pll , j? ?? ??e? ?? * t : r[ : ] c[f] pll ? ? (max) 0 0 0 0 0 lrck pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 n/a - - - - 2 0 0 1 0 bick pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 bick pin 64fs 10k 4.7n 2ms 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms others others n/a table 5. setting of pll mode (*fs: sampling frequency) 2) pll mode w???? * t : ? , j???u mcki ??w ?xz table 6 w ? t?????? * t :u ? rpv?b{ mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a table 6. setting of sampling frequency at pmpll bit = ?1? (reference clock = mcki pin) , j???u lrck or bick ?? ??w ? (lrck or bick ?? ?? ) xz fs3, fs1-0 bits p???? * t :w ? ??lo<^m ( table 7 ) { mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 don?t care 0 0 7.35khz d fs d 8khz (default) 1 0 don?t care 0 1 8khz < fs d 12khz 2 0 don?t care 1 0 12khz < fs d 16khz 3 0 don?t care 1 1 16khz < fs d 24khz 6 1 don?t care 1 0 24khz < fs d 32khz 7 1 don?t care 1 1 32khz < fs d 48khz others others n/a table 7. setting of sampling frequency at pmpll bit = ?1? (reference clock = lrck or bick pin) [ak4343] ms0478-j-02 2010/11 - 26 - pll w????tmmo 1) pll master mode (ain3 bit = ?0?, pmpll bit = ?1?, m/s bit = ?1?) \wt??p pmpll bit = ?0? ? ?1? t`h? pll u??b??pwz bick q lrck x ?l? ? z?z mcko bit = ?1? wqv mcko pin t?x y psm * t :w???u z?^??b{ mcko bit = ?0? w ?xz mcko pin x ?l? ? z?`?b{ ( table 8 ) pll ???z bick q lrck z?x ?l? t???? z?qs??b{7 sw 1 *8 w lrck, bick xz y psmd quk??buz 1fs ?tx y s???ts??b{ ???? * t :?!?b? ?x s pmpll bit = ?0? tb?\qp???? y 6w ? s bick, lrck ? z?^dct ?l? ? z?^d?\qupv?b{ mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin pmpll bit ?0? ? ?1? ? ?l? output ? ?l? output ?l? output pll unlock ( g?? ) ?l? output ? ? ? pll lock ?l? output see table 10 see table 11 1fs output table 8. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (ain3 bit = ?0?, pmpll bit = ?1?, m/s bit = ?0?) \wt??px pmpll bit = ?0? ? ?1? t`h? pll u??b??pwz mcko t?x y psm * t : w???u z?^??b{fw?z pll u??b?q mcko pin t? table 10 p ? r^?h???u z ?^??b{ ``z pll u????tslh ?z dac t?x y s???u z?^??d?{ dacl, dach, dacs bits ? ?0? tb?\qt?? z?????b?\qud pb{ mcko pin pll state mcko bit = ?0? mcko bit = ?1? pmpll bit ?0? ? ?1? ? ?l? output ? pll unlock ( g?? ) ?l? output ? pll lock ?l? output output table 9. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 27 - pll master mode (ain3 bit = ?0?, pmpll bit = ?1?, m/s bit = ?1?) ? ?t? 11.2896mhz, 12mhz , 12.288mhz, 13.5mhz, 24mhz or 27mhz w???? ??`z o ?w pll t? ? mcko, bick, lrck ???? \ r` z?`?b{???? z? (mcko) x ps1-0 bits ( table 10 ) p ? ^?h * t :? z?`z mcko bit p on/off d pb{ bick z?x bcko bit t??z 32fs or 64fs ? ? rb ?\qupv?b{ ( table 11 ) ak4343 dsp or p mcko bick lrck sdti bclk lrck sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk figure 18. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 10. mcko * t : (pll t?? , mcko bit = ?1?) bcko bit bick z? * t : 0 32fs (default) 1 64fs table 11. bick output frequency at master mode [ak4343] ms0478-j-02 2010/11 - 28 - pll slave mode (ain3 bit = ?0?, pmpll bit = ?1?, m/s bit = ?0?) mcki, bick or lrck pin ? ??^??????, jt o ?w pll to ak4343 t ?as???? \ r` ?b{ pll w, j???xz pll3-0 bits to ? b?\qupv?b ( table 5 ) { a) pll , j??? : mcki pin mcko t ?8`h bick, lrck ? ??`?b{ mcko q lrck x ?8b? ?auk??bu? ??d? ? axk??d?{ ???? z? (mcko pin) x ps1-0 bits ( table 10 ) p ? ^?h * t :? z?`z mcko bit p on/off d pb{???? * t :xz fs3-0 bits p ? b?\qupv?b{ ( table 6 ) ak4343 dsp or p mcko bick lrck sdti bclk lrck sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 19. pll slave mode 1 (pll reference clock: mcki pin) [ak4343] ms0478-j-02 2010/11 - 29 - b) pll , j??? : bick or lrck pin fs3-0 bits ? ? b?\qpz 7.35khz 48khz w ?w???? * t :t 0 `?b{ ( table 7 ) a k4343 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs or 64fs figure 20. pll slave mode 2 (pll reference clock: bick pin) ak4343 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs figure 21 pll slave mode 2 (pll reference clock: lrck pin) dac u ?^ (pmdac bit = ?1?) x? ???? (mcki, bick, lrck) ?-?oxmz?d?{\??w? ??u??^?sm ?z o ?t??????s????;`om?h?za ?vuv?z ?^u? ts?d quk??b{????-?? ?x???? y 6 (pmdac bit = ?0?) t`oxi^m{ [ak4343] ms0478-j-02 2010/11 - 30 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) pmpll bit ? ?0? tb?\qpz? ????t?? (ext mode) p ?^`z mcki pin t? pll ?p^ct ?z dac t????? ??pv?b{\wt??x w|???| dac qw i/f t 0`o?? quk? ?b{ ?as???x mcki (256fs, 512fs or 1024fs), bick ( 32fs), lrck(fs) pb{ mcki q lrck x ?8b ? ?auk??bu? ??d? ?axk??d?{ mcki w ?? * t :x fs1-0 bit t?? ? rb?\q ud pb{ ( table 12 ) mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 256fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz table 12. ext slave mode (pmp ll bit = ?0?, m/s bit = ?0?) w mcki * t :w ? ? ????x 3????wh?z dac z?w s/n u?=`?b{ mcki t ??^????? ?w * t :? [?\qpz s/n ?~ 3pv?b{ table 13 x dac z?t? lout/rout pin t `h ?w s/n pb{ mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 512fs 93db 1024fs 93db table 13. relationship between mcki and s/n of lout/rout pins dac u ?^ (pmdac bit = ?1?) x? ???? (mcki, bick, lrck) ?-?oxmz?d?{\??w? ??u??^?sm ?z o ?t??????s????;`om?h?za ?vuv?z ?^u? ts?d quk??b{????-?? ?x???? y 6 (pmdac bit = ?0? t`oxi^m{ ak4343 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 22. ext slave mode [ak4343] ms0478-j-02 2010/11 - 31 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) pmpll bit = ?0? s?| m/s bit = ?1? t ? b?\qpz? ?????t?? (ext master mode) p ?^ `z mcki pin t? pll ?p^ct ?z dac t????? ??pv?b{ ?as???x mcki (256fs, 512fs or 1024fs) pb{ mcki w ?? * t :x fs1-0 bits t?? ? rb?\qud pb ( table 14 ) { mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz (default) 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 256fs 7.35khz 48khz 3 don?t care 1 1 512fs 7.35khz 26khz table 14. ext master mode (p mpll bit = ?0?, m/s bit = ?1?) w mcki * t :w ? ? ????x 3????wh?z dac z?w s/n u?=`?b{ mcki t ??^????? ?w * t :? [?\qpz s/n ?~ 3pv?b{ table 15 x dac z?t? lout/rout pin t `h ?w s/n pb{ mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 83db 512fs 93db 1024fs 93db table 15. relationship between mcki and s/n of lout/rout pins dac u ?^ (pmdac bit = ?1?) x mcki ?-?oxmz?d?{ mcki u??^?sm ?z o ?t???? ??s????;`om?h?za ?vuv?z ?^u? ts?d quk??b{ mcki ?-?? ?x???? y 6 (pmdac bit = ?0?) t`oxi^m{ ak4343 dsp or p mcki bick lrck sdti bclk lrck sdto mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 23. ext master mode bcko bit bick z? * t : 0 32fs (default) 1 64fs table 16. bick output frequency at master mode [ak4343] ms0478-j-02 2010/11 - 32 - 3a??? ?oqj [txz pdn pin t s ?l? ? ??`o?????lo<^m{3a???u???? qz ak4343 w o ??x ?o s8 ?ts??b{ pmdac bit = ?0? ? ?1? t!?b?\qpz dac w s8=???u??^??b{ s8=???x 1059/fs=24ms@fs=44.1khz pb{ s8=??? w dac ?????x o ?p 2?s ??y??w ?0? t{ ^??b{ s8=???u 4?b?qz dac w ? (25/fs=0.5ms@fs=44.1khz) &a?z dac z?x?? ?? ?? ??t pb? ?yts??b{ |???|????????? 4 w??????? ( table 17 ) u dif1-0 bits p ? rpv?b{ ?t??q? msb ????z 2?s ? ?y??w???????pb{|???|?????x?t??q?t??t 0 `?b{?t??px lrck q bick x z?ts?z?t??px ??ts??b{ mode dif1 bit dif0 bit sdti (dac) bick figure 0 0 0 dsp mode t 32fs table 18 1 0 1 ?g? t 32fs figure 28 2 1 0 2g? t 32fs figure 29 (default) 3 1 1 i 2 s ?? t 32fs figure 30 table 17. audio interface format mode 1, 2, 3 pxz sdti x bick w ? n ? p???^??b{ mode 0 (dsp t?? ) pxz bckp, msbs bits t??z|???| i/f w??????!?b?\qupv?b ( table 18 ) { dif1 dif0 msbs bckp audio interface format figure 0 0 lrck ? n ? ?w 1 sw bick ? n ? w ?w bick ? p ? p sdti w msb ???u???^??b{ figure 24 (default) 0 1 lrck ? n ? ?w 1 sw bick ? p ? w ?w bick ? n ? p sdti w msb ???u???^??b{ figure 25 1 0 lrck ? n ? ?w 2 sw bick ? p ? p sdti w msb ?? ?u???^??b{ figure 26 0 0 1 1 lrck ? n ? ?w 2 sw bick ? n ? p sdti w msb ?? ?u???^??b{ figure 27 table 18. audio interface format in mode 0 [ak4343] ms0478-j-02 2010/11 - 33 - lrck bick ( 32fs ) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck (master) (slave) figure 24. mode 0 timing (bckp = ?0?, msbs = ?0?) bick ( 32fs ) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 25. mode 0 timing (bckp = ?1?, msbs = ?0?) bick ( 32fs ) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 lch rch sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 26. mode 0 timing (bckp = ?0?, msbs = ?1?) [ak4343] ms0478-j-02 2010/11 - 34 - bick ( 32fs ) 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 10 13 29 26 218 bick ( 64fs ) 15 0 1 14 15 17 18 30 31 32 33 46 47 49 50 62 63 16 48 15:msb, 0:lsb 1/fs 234 lch rch sdti(i) 0 15 5 8 7 1 432 6 0 15 5 87 1 4 3 2 60 14 14 sdti(i) 15 2 1 0 15 210 14 14 lch rch lrck lrck (master) (slave) figure 27. mode 0 timing (bckp = ?1?, msbs = ?1?) lrck bick(32fs) sdti(i) 0 15 14 110 13 23 76543 210 9 1112131415 0 12 3 15 14 13 1 0 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdti(i) don't care 10 15 210 15 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data figure 28. mode 1 timing lrck bick(32fs) sdti(i) 0 15 14 110 13 23 76543 210 9 1112131415 0 12 3 15 14 13 1 0 15 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdti(i) don't care 15 15 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 10 13 10 15 figure 29. mode 2 timing [ak4343] ms0478-j-02 2010/11 - 35 - lrck bick(32fs) sdti(i) 0 15 14 110 23 76543 210 9 1112131415 0 12 3 15 14 1 0 76543 210 10 9 1112131415 bick(64fs) 0 116 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdti(i) don't care 15 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 21 14 21 8 8 0 0 0 figure 30. mode 3 timing ???? hpf ak4343 x dc |???????;w hpf ? o `om?b{ hpf w??|? * t :x 0.9hz (@fs= 44.1khz) tslos?z???? * t : (fs) t z?`?b{ ???? ak4343 x??????w ????? o `om?b{ mdif1, mdif2 bits = ?0? wqvz inl1-0, inr1-0 bits t??z lin1/lin2/lin3, rin1/rin2/rin3 ?f?g? ~? 8q?\qupv?b{ mdif1, mdif2 bits = ?1? wqvz lin1, rin1, lin2, rin2 pins xf?g? in1 ? , in1+, in2+, in2 ? pins qs?z ) ? ??ud pb ( figure 31) {) ? ??p?;b? ?z table 20 p ?x? 1wmmom?e?tx ??? ??`smpxi^m{ mdif1 bit mdif2 bit inl1 bit inl0 bit inr1 bit inr0 bit lch rch 0 0 0 0 0 0 lin1 rin1 (default) 0 0 0 0 0 1 lin1 rin2 0 0 0 0 1 0 lin1 rin3 0 0 0 1 0 0 lin2 rin1 0 0 0 1 0 1 lin2 rin2 0 0 0 1 1 0 lin2 rin3 0 0 1 0 0 0 lin3 rin1 0 0 1 0 0 1 lin3 rin2 0 0 1 0 1 0 lin3 rin3 0 1 0 0 0 0 lin1 in2+/ ? 0 1 1 0 0 0 lin3 in2+/ ? 1 0 0 0 0 1 in1+/ ? rin2 1 0 0 0 1 0 in1+/ ? rin3 1 1 0 0 0 0 in1+/ ? in2+/ ? others n/a n/a table 19. input path select [ak4343] ms0478-j-02 2010/11 - 36 - register pin ain3 bit mdif1 bit mdif2 bit lin1 in1 ? rin1 in1+ lin2 in2+ rin2 in2 ? min lin3 vcoc rin3 0 0 0 o o o o o - 0 0 1 o x o o o - 0 1 0 o o x o o - 0 1 1 o o o o o - 1 0 0 o o o o o o 1 0 1 o x o o o x 1 1 0 o o x o x o 1 1 1 o o o o x x table 20. handling of line input pins (?-? : n/a; ?x?: signal should not be input.) lin1/in1 ? pin rin1/in1+ pin inl1-0 bits mdif1 bit rin2/in2 ? pin lin2/in2+ pin inr1-0 bits mdif2 bit ak4343 min/lin3 pin vcoc/rin3 pin lineout, receiver-amp, hp-amp, spk-amp gain-amp gain-amp micl3 bit micr3 bit pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit these blocks are not available at pll mode. figure 31. ???? ? ???? ? ?? in1+/ ? pins ?) ? ??z lin2/rin2 pins ?a|??? ??q`o?;b? ?zw 2 t??? ??t ao ~? 8qo?;`oxi^m{ mdif1 bit mdif2 bit inl1 bit inl0 bit inr1 bit inr0 bit lch rch 1 0 0 0 0 1 in1+/ ? rin2 0 0 0 1 0 1 lin2 rin2 table 21.line in path select example [ak4343] ms0478-j-02 2010/11 - 37 - ????? ak4343 x?????? o `om?b{ mgain1-0 bit t?????? ? b?\qupv?b ( table 22 ) { ????e???x mgain1-0 bits = ?00? wqv typ. 60k z mgain1-0 bits = ?01?, ?10?, ?11? wqv typ. 30k pb{ mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +20db (default) 1 0 +26db 1 1 +32db table 22. ????? digital eq/hpf/lpf s? ak4343 px ?????t 0`oz ~?;????za| ez???4 yt| alc w rg??o \qupv?b ( figure 32 ? ) { fil1, fil3, eq xf?g? 1 w iir ????pz???? :? ?t ? pv?b{ alc tmmoxz ?alc ?^ ? w?? `o<^m{ a| ew att x fil3 w :p ?t ? `?b{ ???4 yw???x gn1-0 bits( table 23 ? ) q eq w :w ??dp ? `?b{ fil1, fil3 xf?g? f1as, f3as bits u ?0? wqv hpf ts?z f1as, f3as bits u ?1? wqv lpf ts??b{ fil3 ? off(mute) `z eq, fil1 ? 0db p??^d? ?xzf?g? fil3, eq, fil1 bits ? ?0? t ? `o <^m{???? :? {v?q? ?xz s?? (fil3 x mute) wt??t`ot??lo<^m{ fil3 fil1 eq gain alc : ? f1a13-0 f1b13-0 f1as : ? f3a13-0 f3b13-0 f3as ~?;???? a| e ???4 y : ? eqa15-0 eqb13-0 eqc15-0 +12db 0db 0db -10db mu te (fil3 :p ? ) gn1-0 +24/+12/0db figure 32. digital eq/hpf/lpf gn1 gn0 gain 0 0 0db (default) 0 1 +12db 1 x +24db table 23. gain ?w??? ? (x: don?t care) [ak4343] ms0478-j-02 2010/11 - 38 - [ ???? :w ? tmmo ] 1) fil1, fil3 ? hpf t ? b? ? fs: ???? * t : fc: ??|? * t : f: ?? ?? * t : k: ??? [db] (fil1 w???x 0db t ? `o<^m{ ) ? ? fil1: f1as bit = ?0?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b 13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , ; a : ? ? h(z) = a 1 ? z ? 1 1 + bz ? 1 m(f) = a 2 ? 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b+1)sin (2 f/fs) 1 - b + (b ? 1)cos (2 f/fs) 2) fil1, fil3 ? lpf t ? b? ? fs: ???? * t : fc: ??|? * t : f: ?? ?? * t : k: ??? [db] (fil1 w???x 0db t ? `o<^m{ ) ? ? fil1: f1as bit = ?1?, f1a[13:0] bits =a, f1b[13:0] bits =b fil3: f3as bit = ?1?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f1a13, f1b13, f3a13, f3b 13; lsb=f1a0, f1b0, f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , ; a : ? ? h(z) = a 1 + z ? 1 1 + bz ? 1 m(f) = a 2 + 2cos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (b ? 1)sin (2 f/fs) 1 + b + (b+1)cos (2 f/fs) [ak4343] ms0478-j-02 2010/11 - 39 - 3) eq fs: ???? * t : fc 1 : ?w * t : fc 2 : :w * t : f: ?? ?? * t : k: ??? [db] ( 7 g +12db ?p ? pv?b{ ) ? ? eqa[15:0] bits =a, eqb[13:0] bits =b, eqc[15:0] bits =c (msb=eqa15, eqb13, eqc15; lsb=eqa0, eqb0, eqc0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , ; a : ? ? h(z) = a + cz ? 1 1 + bz ? 1 m(f) = a 2 + c 2 + 2accos (2 f/fs) 1 + b 2 + 2bcos (2 f/fs) (f) = tan ? 1 (ab ? c)sin (2 f/fs) a + bc + (ab+c)cos (2 f/fs) [ t??? z^?h???? :?? :t? 2 : (2 w4 : ) ?!?b? q ] x=( t??? z^?h? :w???? : ) x 2 13 \w x w ? : :?<??? ?`h t : ?? 2 : (2 w4 : ) t!?`o<^m{ ???? : ? ?w msb x ?????pb{ [ ???? :w ? ? ] 1) fil1 ?? ? : fs=44.1khz, fc=100hz w hpf w ? f1as bit = ?0? f1a[13:0] bits = 01 1111 1100 0110 f1b[13:0] bits = 10 0000 0111 0100 2) eq ?? ? : fs=44.1khz, fc 1 =300hz, fc 2 =3000hz, gain=+8db w ? gain[db] +8db fc 1 fc 2 frequency eqa[15:0] bits = 0000 1001 0110 1110 eqb[13:0] bits = 10 0001 0101 1001 eqc[15:0] bits = 1111 1001 1110 1111 [ak4343] ms0478-j-02 2010/11 - 40 - alc ?^ alc bit = ?1? wqvz alc ??t??z alc ?^u????b{ 1. alc ???? ?^ alc ???? ?^px lch, rch w z???wrj?tmp? alc ????u z ? ?? ( table 24 ) ?y qh ?z lmat1-0 bits p ? `h ? ( table 25 ) izz avl, avr ? (l/r ? ) ? ? $tn 0^d?b{ zelmn bit = ?0?( ??u z? ) wqvz alc ???? ?^t?? avl, avr ?u!?^??wxz l/r ?qtf?g???b?t??????`hqvpb{??????x ztm1-0 bits to ? pv?b ( table 26 ) { zelmn bit = ?1?( ??u z? ) wqvz alc ???? ?^t?? avl, avr ?x ` ( *8 : 1/fs) t!? ^??b{???? ?^wn 0?x lmat1-0 bits w ? ttt??c 1 step { pb{ n 0 ?^ 4??p? alc bit ? ?0? t`smv?z6| z???u alc ????u z???yq?yz\ wn 0 ?^x?&^??b{ lmth1 lmth0 alc ????u z?? alc ?? 4;??????? 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 24. alc ????u z????? 4;??????? zelmn lmat1 lmat0 alc ???? att a? 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 4 step 1.500db 0 1 1 8 step 3.000db 1 x x 1step 0.375db table 25. alc ???? att a?w ? (x: don?t care) ?????? ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 26. alc ??????w ? [ak4343] ms0478-j-02 2010/11 - 41 - 2. alc ?? ?^ alc ?? ?^xz wtm2-0 bits p ? ^?h ( table 27 ) 4;??mz\wz z? ??u alc ? ? 4;??????? ( table 24 ) ?yb\qusz?y alc ?? ?^??m?b{ \w alc ? ? ?^x ? ^?h, j?? ( table 29 ) ?p ztm1-0 bits p ? `h ( table 26 ) p??u z ?^ ??msu?z rgain1-0 bits p ? `h ? ( table 28 ) iz avl, avr ? (l/r ? ) ? ? $t ?c^d?b{\ w alc ?? ?^x wtm2-0 bits p ? `h *8p????b{hi`z wtm2-0 bits pw ? ?? ztm1-0 bits pw ? u ?m ?tsmoz ??u??`smqvtxz ztm1-0 bits w ? p alc ?? ? ^u????b{ ?qyzqow avl, avr ?u 30h w ?z rgain1-0 bits = ?01?(2 steps) t ? `osxqz alc ?? ? ^t?lo avl, avr ?x 32h t!?^?z 0.75db(0.375db x 2) ?c^??b{ avl, avr ?u, j?? (ref7-0 bits ) t a`h ?z avl, avr ?w ?cx?m?d?{ ?hz alc ?? 4; t ( ?? 4;??????? ) output signal < ( ????u z?? ) qslom? ?z 4;??x???^??b{fwh?z ( ?? 4;??????? ) > output signal qslht?z 4;w??u??^??b{ ?hz alc ?^x??? qw??t? 0 `h alc tslom?b{??? qw??u ??^ ?h ?z w?? ?^??? ?m???p?? ?^ ( ?????? ?^ ) ??m?b{ ?qyz ` $t gvs;u ??^?h ?z\w ?^t?? gvs;t???h ? ???~ 3b?\qu pv?b{?????? ?^w ^xz rfst1-0 bits t?? ? `?b ( table 30 ) { alc ?? *8 wtm2 wtm1 wtm0 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 27. alc ?? 4;w ? rgain1 rgain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 28. alc ??????w ? [ak4343] ms0478-j-02 2010/11 - 42 - ref7-0 gain(db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 0.375db 00h mute table 29. alc ?? ?^w, j ? ? rfst1 bit rfst0 bit ?? s 0 0 4 (default) 0 1 8 1 0 16 1 1 n/a table 30. ?????? s ? [ak4343] ms0478-j-02 2010/11 - 43 - 3. alc ?^ ? q? table 31 xz alc ? ?pb{ fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits. 001 32ms 011 23.2ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db avl7-0, avr7-0 gain of avol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times alc alc enable 1 enable 1 enable table 31. alc ? ? alc ?^ xz ?<w????w!??e-`?b{ \??w????!?b? ?xz alc ?^? 4? (alc bit = ?0? ?hx pmdac bit = ?0?) `ot??lo<^m{ ~ lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain1-0, ref7-0, zelmn, rfst1-0 w??? manual mode * the value of avol should be the same or smaller than ref?s wr (ztm1-0, wtm2-0, rfst1-0) wr (ref7-0) wr (avl/r7-0) wr (lmat1-0, rgain0, zelmn, lmth0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 32ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? (1) addr=06h, data=14h (2) addr=08h, data=e1h (5) addr=07h, data=01h (3) addr=09h&0ch, data=e1h alc operation wr (rgain1, lmth1) (4) addr=0bh, data=00h wr : write figure 33. alc ?^ ? q? [ak4343] ms0478-j-02 2010/11 - 44 - alc ???????? ( ???t?? ) alc bit = ?0? wqvz alc ?w???????x???t??ts??b{\wt??x?<w ?t?;`?b{ 1. ???r ??z alc ?^tb?? ? (ztm1-0, lmth1-0 bits sr ) ??o ?{ 2. ???? * t :w!?t pmz??????? *8sr alc ?^tb??!?? ?o ?{ alc ????????w????x avl7-0, avr7-0 bits p ? `?b ( table 32 ) {???!?z l/r ?qt??u z ?^??m?b{??????x ztm1-0 bits p ? b?\qup v?b{ alc ??;`sm ?x avl7-0 = avr7-0 bits = 91h (0db) t ? `o<^m{ avl7-0 avr7-0 gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 32. alc ????????w ? ? [ak4343] ms0478-j-02 2010/11 - 45 - avl7-0, avr7-0 bits w {v?? zo?o ?xz??????? w?kzo?l o<^m{ t w?kzsmp {v???oqz????u?s???^???? u ~? 8???d?{hi`z {v?? ?u 2sq ?a ?w ?x {v?u1^?z?? ??x???^?smwpz???????? ymp {v???o\qup v?b{ a lc bit a lc status disable enable disable a vl7-0 bits e1h(+30db) a vr7-0 bits c6h(+20db) internal avl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) internal avr c6h(+20db) e1(+30db) --> f1(+36db) c6h(+20db) (1) (2) figure 34. alc ?^ w avol ?^? (1) alc ??t avl q avr w ?u?slom? ?xz avl w ?u??? ?ts??b{ alc bit = ?1? ? {v?pt? avl7-0 bits w ?p alc ?^???b??pw 4jx7 gp?? 4; (wtm2-0 bits) + ?????? (ztm1-0 bits) pb{ (2) alc ?^ xz avl, avr w? (09h, 0ch) t {v???lo? s^??d?{ alc u disable ^?h?z???hx??????tfw ?u s^??b{6 s alc ? enable b ? ?xz alc bit = ?0? w?z??????? w?zo alc bit = ?1? ? ? `o <^m{ [ak4343] ms0478-j-02 2010/11 - 46 - ?????3???????? iir ????t?? 3 * t : (32khz, 44.1khz, 48khz) 0 w?????3???? (tc=50/15 s ? q ) ? o `om?b{ ?????t 0`oz dem1-0 bits p ? r^?h * t :w?????3????u?ts ??b ( table 33 ) { dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 33. ?????3???? ??s? bst1-0 bits ?????b?\qpz dac t? ??^?h ??? z?b?\qupv?b ( table 34 ) {?hz bst1-0 bits = ?01?(min) t{ b?\qpz????? z?w dc ??;???? 47 f ?p ?^xb?\qupv?b{??^?h ??u??-??? qh ?z dac t?w z?u ???`?b{ figure 35 x ? 20db w ????? ??`h ?w???w ? qpb{ boost filter (fs=44.1khz) -25 -20 -15 -10 -5 0 10 100 1000 10000 frequency [hz] level [db] max mid min figure 35. ?? * t : (fs=44.1khz) bst1 bst0 mode 0 0 off (default) 0 1 min 1 0 mid 1 1 max table 34. ?????? [ak4343] ms0478-j-02 2010/11 - 47 - z???? ak4343 x mute ?? 0.5db a?z 256 ??w??? ?q???? z???? (datt) ? o `?b{\w???x dac w 2 ?tk?z ?????? +12db t? ? 115db ?pn 0z?hx???` ?b{ dvolc bit ? ?1? tb?qz dvl7-0 bits p lch, rch w???? ?t????pv?b{ dvolc bit u ?0? w ?z lch, rch w???x ?qt????pv?b{?hz att ? w -?x 1061 ? ??hx 256/fs p1?? -?`?b{ -?a?x dvtm bit p ? `?b{ dvtm bit = ?0? wqvz 00h(+12db) t? ffh(mute) ?ptx 1061/fs(24ms@fs=44.1khz) tt??b{ dvl/r7-0 gain step 00h +12.0db 01h +11.5db 02h +11.0db : : 18h 0db (default) : : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 35. digital volume code table dvl/r7-0 bits = 00h t? ffh ?pw -? dvtm bit ? ? fs=8khz fs=44.1khz 0 1061/fs 133ms 24ms (default) 1 256/fs 32ms 6ms table 36. z????w -? ? [ak4343] ms0478-j-02 2010/11 - 48 - 1?????; dac ??w???? ?t1?????; ? o `?b{1?????x smute bit p???? pv?b{ smute bit ? ?1? tb?q dvtm bit p ? `h???p ?????u ? (?0?) ?p?a?3? ?^??b{ smute bit ? ?0? tb?q ? y 6ur ?^?z ? t? dvtm bit p ? `h???pz dvl/r7-0 bits p ? `h??? ??p ?<`?b{1????????z dvtm bit p ? `h???? ot r ?^??q?a?3??u ?^?z ?a???pz dvl/r7-0 bits p ? `h??? ??p ?< `?b ( figure 36 ) { smute bit a ttenuation dvtm bit dvl/r7-0 bits - dvtm bit gd gd (1) (2) (3) a nalog output figure 36. 1?????; (1) dvtm bit p ? `h???p ?????u ? (?0?) ?p?a?3??^??b{ (2) ???? ??t 0b???? z?x ? (gd) ??j?b{ (3) 1????????z dvtm bit p ? `h???? otr ?^??q?a?3??u ?^?z ?a???pz dvl/r7-0 bits p ? `h??? ??p ?<`?b{ [ak4343] ms0478-j-02 2010/11 - 49 - ?????3?? : a| ?? (lin2/rin2 pins, ain3 bit = ?1?: lin3/rin3 pins) pmainl2=pmainr2 bits = ?1? wqvz lin2/rin2 pins x?????3??;a| ??q`o?;pv ?b{ lins2 bit s?| rins2 bit ? ?1? tb?q lin2/rin2 pins t? ??^?h ???e???t? z? `z linh2 bit s?| rinh2 bit ? ?1? tb?q???????t? z?`z linl2 bit s?| rinr2 bit ? ?1? tb?qa|??? z?t? z?b?\qupv?b{ ain3 bit = ?1? wqvz min/vcoc pins xf?g? lin3/rin3 pins ts??b{ \wqv pll x?;pv?d?{ pmainl3=pmainr3 bits = ?1? wqvz lin3/rin3 pins x?????3??;a| ??q`o?;pv ?b{?hz pmmicl=pmmicr=micl3=micr3 bits = ?1? wqvz??3??pv? ??u lin3/rin3 pins ??t? gain-amp z?t ~? 8???b{ lins3 bit s?| rins3 bit ? ?1? tb?q lin3/rin3 pins t? ??^ ?h ???e???t? z?`z linh3 bit s?| rinh3 bit ? ?1? tb?q???????t? z ?`z linl3 bit s?| rinr3 bit ? ?1? tb?qa|??? z?t? z?b?\qupv?b{ lin3/rin3 pins w ????e???xz micl3=micr3 bits = ?0? p?;`om? ?z mgain1-0 bits = ?00? wqv typ. 30k z mgain1-0 bits = ?01?, ?10?, ?11? wqv typ. 20k pb{ micl3=micr3 bits = ?1? p?;`o m? ?z mgain1-0 bits = ?00? wqv typ. 60k z mgain1-0 bits = ?01?, ?10?, ?11? wqv typ. 30k pb{ w??? (typ) ? table 37 , table 38 , table 39 , table 40 t?`?b{ lin1/in1 ? pin rin1/in1+ pin inl1-0 bits mdif1 bit rin2/in2 ? pin lin2/in2+ pin inr1-0 bits mdif2 bit ak4343 min/lin3 pin vcoc/rin3 pin lineout, receiver-amp, hp-amp, spk-amp gain-amp gain-amp micl3 bit micr3 bit pmainl3 bit pmainr3 bit pmainl2 bit pmainr2 bit these blocks are not available at pll mode. figure 37. ?????3??s? ( a| ?? ) [ak4343] ms0478-j-02 2010/11 - 50 - pmainl2 bit pmainr2 bit lout/rcp pin, rout/rcn pin linl2/rinr2 hpl, hpr pin linh2/rinh2 spp, spn pin lins2/rins2 lin2/rin2 figure 38. ?????3??s? (lin2/rin2) pmainl3 bit pmainr3 bit linl3/rinr3 linh3/rinh3 lins3/rins3 lin3/rin3 lout/rcp pin, rout/rcn pin hpl, hpr pin spp, spn pin figure 39. ?????3??s? (lin3/rin3 : pll ?; ?d ) lovl bit lin2/rin2/lin3/rin3 ? lout/rout 0 0db (default) 1 +2db table 37. lin2/rin2/lin3/rin3 input ? lout/rout output gain (typ) lovl bit lin2/rin2/lin3/rin3 ? rcp/rcn 0 0db (default) 1 +2db table 38. lin2/rin2/lin3/rin3 input ? rcp/rcn output gain (typ) hpg bit lin2/rin2/lin3/rin3 ? hpl/hpr 0 0db (default) 1 +3.6db table 39. lin2/rin2/lin3/rin3 input ? headphone-amp output gain (typ) lin2/rin2/lin3/rin3 ? spp/spn spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 ? 1.59db +0.41db (default) 01 +0.41db +2.41db 10 +4.63db +6.63db 11 +6.63db +8.63db table 40. lin2/rin2/lin3/rin3 input ? speaker-amp output gain (typ) [ak4343] ms0478-j-02 2010/11 - 51 - ?????3?? : t?? ?? (ain3 bit = ?0?: min pin) ain3 bit = ?0? wqvz min pin x?????3???wt?? ??q`o?;pv?b{ pmmin bit = ?1? wz mins bit ? ?1? tb?q min pin t? ??^?h ???e???t? z?`z minh bit ? ?1? tb ?q???? ???t? z?`z minl bit ? ?1? tb?qa|??? z?t? z?b?\qupv ?b{ ??^?? ??x r i p?? e tpv?b{ r i = 20k w??? (typ) ? table 41 , table 43 , table 44 t ?`?b{\w???xz r i w ?t s z?`?b{ min ri lout/rcp pin, rout/rcn pin minl hpl, hpr pin minh spp, spn pin mins figure 40. block diagram of min pin lovl bit min ? lout/rout 0 0db (default) 1 +2db table 41. r i = 20k z min ?? ? lout/rout z???? (typ) lovl bit min ? rcp/rcn 0 0db (default) 1 +2db table 42. r i = 20k z min ?? ? rcp/rcn z???? (typ) hpg bit min ? hpl/hpr 0 ? 20db (default) 1 ? 16.4db table 43. r i = 20k z min ?? ? ????? z???? (typ) min ? spp/spn spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +4.43db +6.43db (default) 01 +6.43db +8.43db 10 +10.65db +12.65db 11 +12.65db +14.65db table 44. r i = 20k z min ?? ? e? z???? (typ) [ak4343] ms0478-j-02 2010/11 - 52 - a|??? z? (lout/rout pins) dacl bit ? ?1? tb?qz dac w lch, rch ???f?g? lout, rout pins t?3?????p z?`? b{ dacl bit ? ?0? tb?qz z?? off tb?\q?d pb{\wz lout, rout pins x vcom ?y ? z?`?b{?hz ?y ?x min. 10k pb{ pmlo=lops bits = ?0? tb?qz???? y 6ts ? avss t 100k ( typ) p???^??b{ lops bit = ?1? qb?qz???t??ts??b{? hz lops bit = ?1? q`oz pmlo bit p????w on/off ??oqz on/off t c \b??;? ?nb?\qupv?b{\wqvz figure 42 t?b?ot c ???za|??? z?w???? 20k w ?p???`oxi^m{qj u?s?|q<u?wx c=1 f, avdd=3.3v wqvz7 g 300ms pb{a|??? z?xz pmlo bit = ?1? tm lops bit = ?0? p???? y 6qs??b{ a|??? z?w???x lovl bit p ? `?b{ dac ?dacl? lout pin rout pin ?lovl? figure 41. a|??? z? lops pmlo mode lout/rout pin 0 ???? pull-down to avss (default) 0 1 ?^ ?^ 0 ??? fall down to avss 1 1 ??? rise up to vcom table 45. a|??? z?wt?? ? (x: don?t care) lovl gain z? ?y (typ) 0 0db 0.6 x avdd (default) 1 +2db 0.757 x avdd table 46. a|??? z???? ? lout rout 1 f 220 20k figure 42. a|??? z?? ?zs? ( ?; ?ns??; ) [ak4343] ms0478-j-02 2010/11 - 53 - ?a|??? z?????3?-? ( ?; ?ns??; ) ? pmlo bit lo p s bit lout, rout pins (1) (2) norm al output (3) (4) (5) (6) 300 m s 300 m s figure 43. a|??? z?????3?-? ( ?; ?ns??; ) (1) ???t??? on `?b{ lops bit = ?1? (2) ?????r ?`?b{ pmlo bit = ?1? lout, rout pins uqj u??b{qj u?x c=1 f, avdd=3.3v wqv 200ms (max 300ms) pb{ (3) lout, rout pins uqj ulh?p???t???r ?`?b{ lops bit = ?0? a|??? z?ud ts??b{ (4) ???t??? on `?b{ lops bit = ?1? (5) ????t ? `?b{ pmlo bit = ?0? lout, rout pins uqj<u??b{qj<u?x c=1 f, avdd=3.3v wqv 200ms (max 300ms) pb{ (6) lout, rout pins uqj<ulh?p???t???r ?`?b{ lops bit = ?0? [ak4343] ms0478-j-02 2010/11 - 54 - ?a|??? z?w??3??s?? ain3 bit = ?0? wqvzw on/off xf?g? dacl, minl, linl2, rinr2 bits p ? `?b{ min wc????x? ? ?? ? 20k wqv 0db(typ)@lovl bit = ?0? pb{ lin2/rin2/dac wc????x 0db(typ)@lovl bit = ?0? pb{ lin2 pin 0db m i x linl2 bit min pin 0db minl bit 0db dacl bit dac lch lout pin figure 44. lout w??3??s? (ain3 bit = ?0?, lovl bit = ?0?) rin2 pin 0db m i x rinr2 bit min pin 0db minl bit 0db dacl bit rout pin dac rch figure 45. rout w??3??s? (ain3 bit = ?0?, lovl bit = ?0?) ain3 bit = ?1? wqvzw on/off xf?g? dacl, linl2, rinr2, linl3, rinr3, micl3, micr3 bits p ? `?b{c????xmc?w? 0db(typ) pb{ lin2 pin 0db m i x linl2 bit lin3 pin 0db linl3 bit 0db dacl bit lout pin micl3 bit lin1 pin gain-amp lch dac lch *these blocks are not available at pll mode. figure 46. lout w??3??s? (ain3 bit = ?1?, lovl bit = ?0?) rin2 pin 0db m i x rinr2 bit rin3 pin 0db rinr3 bit 0db dacl bit rout pin micr3 bit rin1 pin gain-amp rch dac rch *these blocks are not available at pll mode. figure 47. rout wc?s? (ain3 bit = ?1?, lovl bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 55 - 3??? (rcp/rcn pins) rcv bit = ?1? wqvz lout/rout pins xf?g? rcp/rcn pins ts??b{ dac ?hx lin2/rin2/lin3/rin3 t?w ???t?? ?? [(l+r)/2] t!?`z rcp/rcn pins t? btl z?`?b{? hz ?y ?x min. 32 pb{ pmlo bit = ?0? tb?q???? y 6ts?z rcp/rcn pins x hi-z ts ??b{ pmlo bit = ?1?, lops bit = ?1? qb?qz???t??ts??b{ pmlo bit = ?1?, lops bit = ?0? qb?qz????`?b{3???x lovl bit to???? e tb?\qupv?b{ dac ?dacl? rcp pin rcn pin ?lovl? figure 48. mono receiver output lovl gain output voltage (typ) 0 +6db 0.59 x avdd @ ? 6dbfs (default) 1 +8db 0.59 x avdd @ ? 8dbfs table 47. mono receiver output volume setting pmlo lops mode rcp rcn 0 x power-down hi-z hi-z (default) 1 power-save hi-z vcom 1 0 normal operation normal operation normal operation table 48. receiver-amp mode setting (x: don?t care) pmlo bit lops bit rcp pin rcn pin vcom vcom hi-z hi-z hi-z hi-z >1ms >0 figure 49. power-up/power- down timing for receiver-amp [ak4343] ms0478-j-02 2010/11 - 56 - ?3? z?w??3??s?? ain3 bit = ?0? wqvzw on/off xf?g? dacl, minl, linl2, rinr2 bits p ? `?b{ min wc????x? ? ?? ? 20k wqv +6db(typ)@lovl bit = ?0? pb{ lin2/rin2/dac wc????x 0db(typ)@lovl bit = ?0? pb{ lin2 pin 0db m i x linl2 bit min pin 0db rinr2 bit +6db minl bit dac lch rcp/n pin rin2 pin 0db dacl bit 0db dacl bit dac rch figure 50. 3?w??3??s? (ain3 bit = ?0?, lovl bit = ?0?) ain3 bit = ?1? wqvzw on/off xf?g? dacl, linl2, rinr2, linl3, rinr3 micl3, micr3 bits p ? `?b{c????xb?owp 0db(typ)@lovl bit = ?0? pb{ lin2 pin 0db m i x linl2 bit lin3 pin 0db linl3 bit 0db dacl bit rcp/n pin micl3 bit lin1 pin gain-amp lch dac lch rin2 pin 0db rinr2 bit rin3 pin 0db rinr3 bit micr3 bit rin1 pin gain-amp rch 0db dacl bit dac rch *these blocks are not available at pll mode. *these blocks are not available at pll mode. figure 51. 3?w??3??s? (ain3 bit = ?1?, lovl bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 57 - ??????? (hpl/hpr pins) ???????w ?ox hvdd t???^??b{t? ?yx hvdd/2@vbat bit = ?0? pb{ ?y ?x 16 (min) pb{ z? ?yx hpg bit p ~? 8q?\qupv?b ( table 49 ) { hpg bit 0 1 output voltage [vpp] 0.6 x avdd 0.91 x avdd table 49. ?????w z? ?y hpmtn bit ? ?0? tb?qz???????wt? ?y? hvss tqj<[?b{ hpmtn bit ? ?1? t b?qt? ?y? hvdd/2@vbat bit = ?0? tqj [?b{???w-wh?tz mutet pin q? ???t???? ? `?b{qj [?qj<[ :x hvdd s?| mutet pin w???t z?`?b{ ? : mutet pin w??? c=1 f, hvdd=3.3v w ? ~ ???????qj [?qj<[ : : 100ms(typ), 250ms(max) ~ ?tqj<u??pw : 500ms(max) pmhpl, pmhpr bits ? ?0? tb?\qpz???????? ?t????b?\qupv?b{ \wz hpl, hpr pins x ?l? (hvss) ts??b{ pmhpl bit, pmhpr bit (1) (2) (4) (3) hpmtn bit hpl pin, hpr pin figure 52. ???????w???????3?-? (1) ???????w???? (pmhpl, pmhpr bits = ?1?) { z?x hvss w??pb{ (2) ???????wt? ?yqj [ (hpmtn bit = ?1?) { (3) ???????wt? ?yqj<[ (hpmtn bit = ?0?) { (4) ???????w???? (pmhpl, pmhpr bits = ?0?) { z?x hvss ts??b{?;w- wh?z???????wt? ?yu ?t<ulot?????`oxi^m{ [ak4343] ms0478-j-02 2010/11 - 58 - boost=off z???????w? ? ?q???p??|? * t : (fc) u>???b{ ??? ;b?\qp??|? * t :? ???3? ?b?\qupv?b{ table 50 t? ? ?q? ??t|??|? * t : (fc) wqfww z?????`?b{ ``z?????w r l x 16 q`?b{ z???x hvdd=3.0, 3.3, 5v w ?pb{ ???????w z?x 0.6 x avdd (vpp)@hpg bit = ?0?, 0.91 x avdd (vpp)@hpg bit = ?1? pb{ ? ?zw r u 12 ?<w ?xz???????u c b?d quk??bwpz c w-s? (0.22 f 20% w???q 10 ? 20% w ? ) ?mzo<^m{ ak4343 hp-amp 16 headphone 10 0.22 c r figure 53. ???????w? ?zs?? output power [mw]@0dbfs hpg bit r [ ] c [ f] fc [hz] boost =off fc [hz] boost =min fs=44.1khz hvdd=3.0v avdd=3.0v hvdd=3.3v avdd=3.3v hvdd=5v avdd=3.3v 220 45 17 0 100 100 43 25.3 30.6 30.6 100 70 28 6.8 47 149 78 12.5 15.1 15.1 100 50 19 0 16 47 106 47 6.3 7.7 7.7 220 45 17 0 100 100 43 51 ( note 39 ) 62 ( note 39 ) 70 22 62 25 1 100 10 137 69 1.1 1.3 1.3 table 50. ? ?zs?? note 38. 16 ?y zpw z? ??pb{ note 39. z? ??x???`?b{ ????????w psrr ? 3 ?w3atsmo hvdd ??a? ?yt? ???b? ?z rf ??u??????? w ? qt1?t?b ?uk??b{ vbat bit = ?1? t ? b?qz hvdd t o t^????t 0b? ???????w psrr ?~ 3b?\qupv?b{\wqv???????wt? ?yx 0.64 x avdd(typ) pb{ avdd=3.3v zt? ?yx 2.1v qs?wpz hvdd w ?yu 4.2v ???<ulh ?z z? ??u???`?bxs??b{ vbat bit 0 1 common voltage [v] 0.5 x hvdd 0.64 x avdd table 51. ???????wt? ?y [ak4343] ms0478-j-02 2010/11 - 59 - ?????? z?w??3??s?? ain3 bit = ?0? wqvzw on/off xf?g? dach, minh, linh2, rinh2 bits p ? `?b{ min wc????x? ? ?? ? 20k wqv ? 20db(typ)@hpg bit = ?0? pb{ lin2/rin2/dac wc????x 0db(typ)@hpg bit = ?0? pb{ lin2 pin 0db m i x linh2 bit min pin ? 20db minh bit 0db dach bit dac lch hpl pin figure 54. hpl w??3??s? (ain3 bit = ?0?, hpg bit = ?0?) rin2 pin 0db m i x rinh2 bit min pin ? 20db minh bit 0db dach bit dac rch hpr pin figure 55. hpr w??3??s? (ain3 bit = ?0?, hpg bit = ?0?) ain3 bit = ?1? wqvzw on/off xf?g? dach, linh2, rinh2, linh3, rinh3, micl3, micr3 bits p ? `?b{c????xmc?w? 0db(typ) pb{ lin2 pin 0db m i x linh2 bit lin3 pin 0db linh3 bit 0db dach bit hpl pin micl3 bit lin1 pin gain-amp lch dac lch *these blocks are not available at pll mode. figure 56. hpl w??3??s? (ain3 bit = ?1?, hpg bit = ?0?) rin2 pin 0db m i x rinh2 bit rin3 pin 0db rinh3 bit 0db dach bit hpr pin micr3 bit rin1 pin gain-amp rch dac rch *these blocks are not available at pll mode. figure 57. hpr wc?s? (ain3 bit = ?1?, hpg bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 60 - e??? (spp/spn pins) e???; ?o hvdd w ?y c?x 2.6v 5.25v w c?p ?t ? b?\qud pb{ e? ??????e? y ?e? ?y ? (min) 8 50 ( note 19 ) ?y0? (max) 30pf 3 f ( note 19 ) note 19. 31hfigure 58 tsmoz load impedance x3??? ? (rseries) q 1khz tsz?y ?e?w?? e???w r??e???pb{ load capacitance xy ?e?w0? r pb{y ?e?? ?;b? ?z spp, spn pin tf?g? 10 ? w3??? ?? ? `o<^m{ table 52. e?w dac s?| lin2/rin2/lin3/rin3 t?w ???t?? ?? [(l+r)/2] t!?`ze???t ??`? b{\we???xz btl ? t??t?? z?pz spkg1-0 bits to???? e t b?\qup v?b{e???t?w z???x avdd s?| spkg1-0 bits t??>???b{ ??? spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +4.43db +6.43db (default) 01 +6.43db +8.43db 10 +10.65db +12.65db 11 +12.65db +14.65db table 53. spk-amp ??? spk-amp z? (dac ?? =0dbfs) avdd hvdd spkg1-0 bits alc bit = ?0? alc bit = ?1? (lmth1-0 bits = ?00?) 00 3.30vpp 3.11vpp 01 4.15vpp ( note 40 ) 3.92vpp 10 6.75vpp ( note 40 ) 6.37vpp ( note 40 ) 3.3v 11 8.50vpp ( note 40 ) 8.02vpp ( note 40 ) 00 3.30vpp 3.11vpp 01 4.15vpp 3.92vpp 10 6.75vpp ( note 40 ) 6.37vpp ( note 40 ) 3.3v 5.0v 11 8.50vpp ( note 40 ) 8.02vpp ( note 40 ) note 40. ??u???`smq> `h ?w z???pb{?mtxz dac t? 0dbfs w ??u z? ^?h ?z ??u???`?b{???^dsmh?tx dvol st?? dac t?w z? ???<[oz spk-amp t?w z?? 4.0vpp(hvdd=3.3v) ?hx 6.0vpp(hvdd=5v) ?<thq? ? auk??b{ table 54. spk-amp z??? [ak4343] ms0478-j-02 2010/11 - 61 - ?e?6 \w alc ? ?? fs=44.1khz register name comment data operation lmth1-0 limiter detection level 00 ? 2.5dbfs zelmn limiter zero crossi ng detection 0 enable ztm1-0 zero crossing timeout period 10 11.6ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits 011 23.2ms ref7-0 maximum gain at recovery operation c1h +18db avl7-0, avr7-0 gain of avol 91h 0db lmat1-0 limiter att step 00 1 step rgain1-0 recovery gain step 00 1 step alc alc enable 1 enable table 55. e?6 \w alc ? ? ?y ?e??;w ?? :? y ?e??; xz figure 58 t?b?ot3??? ? (10 ? ) ? spp pin, spn pin qe?wt ?`oxi^m{?hz? ?t?y?ucq??hqvy ?e?ui ??? c \b?wpzfw 0f t figure 58 t?b?ote?q gnd t????|??? ?`oxi^m{????|?? x?<w e??hb?w??;`oxi^m{ 0.92 x hvdd ????|?? ( figure 58 w zd) w?? ?y hvdd+0.3v ex) hvdd = 5.0v w : 4.6v zd 5.3v ?qyz?? ?y 5.1v(min ? 4.97v, max ? 5.24v) w????|??u?;d pb{ spp spk-amp spn 10 10 zd zd figure 58. spk z?s? ( y ?e?q ? b? ? ) [ak4343] ms0478-j-02 2010/11 - 62 - ?e???w????3?-?? pmspk bit pe???? power-up/down pv?b{ pmspk bit u ?0? w ?z spp, spn pin x hi-z ts? ?b{ pmspk bit u ?1? wz sppsn bit ? ?0? tb?qe???x???t??ts??b{\ wz spp pin x hi-z z spn pin x hvdd/2 ? z?`?b{ ?o d ??z pdn pin ? ?l? t? ?h? t!?`z pmspk bit ? ?1? tb?qz spp, spn pin x???t?? pqj u??b{\wz spp pin x hi-z tz spn pin x hvdd/2 ts??buz???t??pq j [?qz???? ?n^d?\qupv?b{?hz power-down (pmspk bit=?0?) ???? t???& b?\qpz ?7t???? ?n^d?\qupv?b{ pmspk sppsn mode spp spn 0 x ???? hi-z hi-z (default) 0 ??? hi-z hvdd/2 1 1 ?^ ?^ ?^ table 56 e???wt?? ? (x: don?t care) pmspk bit sppsn bit spp pin spn pin hvdd/2 hvdd/2 hi-z hi-z hi-z hi-z >1ms >0 figure 59. power-up/power-down timing for speaker-amp [ak4343] ms0478-j-02 2010/11 - 63 - ?e? z?w??3??s?? ain3 bit = ?0? wqvzw on/off xf?g? dacs, mins, lins2, rins2 bits p ? `?b{ min wc????x? ? ?? ? 20k wqv +4.43db(typ)@spkg1-0 bits = ?00?, alc bit = ?0? pb{ lin2/rin2/dac wc????x ? 1.59db(typ)@spkg1-0 bits = ?00?, alc bit = ?0? pb{ lin2 pin ? 1.59db m i x lins2 bit min pin rins2 bit mins bit dac lch spp/n pin rin2 pin dacs bit dacs bit dac rch ? 1.59db +4.43db ? 1.59db ? 1.59db figure 60. e?w??3??s? (ain3 bit = ?0?, spkg1-0 bits = ?00?, alc bit = ?0?) ain3 bit = ?1? wqvzw on/off xf?g? dacs, lins2, rins2, lins3, rins3 bits p ? `?b{ c????xb?owp ? 1.59db (typ)@spkg1-0 bits = ?00?, alc bit = ?0? pb{ lin2 pin m i x lins2 bit lin3 pin lins3 bit dacs bit spp/n pin micl3 bit lin1 pin gain-amp lch dac lch rin2 pin rins2 bit rin3 pin rins3 bit micr3 bit rin1 pin gain-amp rch dacs bit dac rch ? 1.59db ? 1.59db ? 1.59db ? 1.59db ? 1.59db ? 1.59db *these blocks are not available at pll mode. *these blocks are not available at pll mode. figure 61. e?w??3??s? (ain3 bit = ?1?, spkg bits = ?00?, alc bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 64 - 3???????????? (1) 3 3???????t?? (i2c pin = ?l?) ? ? x 3 3??? i/f e? (csn, cclk, cdti) p {v???m?b{ i/f w???x chip address (1bit, ?1? { ), read/write (1bit, ?1? { ), register address (msb first, 6bits) q control data (msb first, 8bits) p? r^??b{??? ? x cclk w ? ? p???? z?`z ! ? x ? ? p ???b{? ??w {v?x csn w ? ? ? 16 sw cclk ? ? p?ts??b{ cclk w???e??x 5mhz (max) pb{ pdn pin = ?l? p?w ?x???^??b{ csn cclk 0 1 2 3 4 5 67891011 12 13 14 15 cdti c1 a 5 a 2 a 3 a 1 a 0 a 4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1: chip address; fixed to ?1? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a 5-a0: register address d7-d0: control data ?1? ?1? figure 62. 3????????????????? [ak4343] ms0478-j-02 2010/11 - 65 - (2) i 2 c ????t?? (i2c pin = ?h?) ak4343 w i 2 c t??w????xz? t?? (max:400khz) t 0 `om?b{ sda, scl pins w ??? ?w ? ?x (dvdd+0.3)v ?<t`o<^m{ (2)-1. write ?? i 2 c t??tsz???? {v?3?-?x figure 63 t?^??b{ w ic ?w??txz 7 st?? e (start condition) ? ??`?b{ scl ???u ?h? wt sda ???? ?h? t? ?l? tb?qz ?? eu^???b ( figure 69 ) {?? ew?z???u ?^??b{\w??x 7 ?? ?t?? r^?z 8 ???tx???m2??? (r/w) u v?b{ ? 6 ???x ?001001? { zw 1 ???x??b? ic ? ?h?w?????pz cad0 pin t?? ? ^??b ( figure 64 ) {?? u ?`h ?z ak4343 x? y t (acknowledge) ? \ r`z??u??^??b{?x? y t; w????? \ r`z sda ????rl`sz?ys??d? ( figure 70 ) { r/w bit u ?0? w ?x? ?? {v?z r/w bit u ?1? w ?x??? ?? z`??m?b{ h 2 ??x?? ( ??? ) pb{??x 8 ???z msb first p? r^?z ? 2 ???x ?0? { pb ( figure 65 ) { h 3 ????x???????pb{ ???????x 8 ???z msb first p? r^??b ( figure 66 ) { ak4343 xz??w ! ???b?h|t? y t? \ r`?b{ ??? 8 xz ?c?u \ rb? - e (stop condition) t?lo 4?`?b{ scl ???u ?h? w t sda ???? ?l? t? ?h? tb?qz - eu^???b ( figure 69 ) { ak4343 x :w??w???? st {v?\qupv?b{???? 1 ?? lh?z - e? ?c?t???? ?qz??u ? $t????y??^?zw???xw?? t ^??b{?? ?24h? t???? {v?i?z^?tw??t {v?i ?tx?? ?00h? t???u {v???b{ ???u ?h? wxz sda ???w y 6x psz?ys??d?{??????u ?h? q ?l? wp y 6?!?pv?wxz scl ???w??? ??u ?l? wtv???b ( figure 71 ) { scl ???u ?h? w t sda ????!?b?wxz?? ez - e? ??b?qvw?pb{ sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 63. i 2 c t??w??? 8 3?-? 0 0 1 0 0 1 cad0 r/w (cad0 xe?t?? ? ) figure 64. h 1 ??w? r 0 0 a5 a4 a3 a2 a1 a0 figure 65. h 2 ??w? r d7 d6 d5 d4 d3 d2 d1 d0 figure 66. h 3 ????w? r [ak4343] ms0478-j-02 2010/11 - 66 - (2)-2. read ?? r/w bit u ?1? w ?z ak4343 x read ?^??m?b{| ^?h??w???u z?^?h?z ?u - e? ?c? y t? \ rb?qz??u ? $t????y??^?zw?? w???? ?? zb\qupv?b{?? ?24h? w???? ?? z`h?z^?tw??? ?? zb ?tx?? ?00h? w???u ?? z^??b{ ak4343 x???????q??????w 2 mw read ????lom?b{ (2)-2-1. ??????? ak4343 x o ?t??????los?z???????px\w??p| ^?h ??w???? ?? z`?b{ o ?w????x7?t??`h??ww?? ??-?`om?b{?qyz7?t?? (read p? write p? ) `h??u ?n? pk?zfw? ?????????lh ?z?? ?n+1? w???u ?? z^??b{??????? pxz ak4343 x read ??w??? (r/w bit = ?1?) w ??t 0`o? y t? \ r`zw? ??t? o ?w????p| ^?h???? z?`hwj o ???? 1 m????y??` ?bg???u z?^?h?j?u? y t? \ rdc - e? ?qz read ?^x 4?`?b{ sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 67. ??????? (2)-2-2. ???????? ????????t?? ?w??w???? ?? zb\qupv?b{??????? ?x read ??w??? (r/w bit = ?1?) ? ??b? 2tz???w write ??? ??b? ?auk ??b{ ????????px7 st?? e? ??`z t write ??w??? (r/w bit = ?0?) z ?? zb??? q ??`?b{ ak4343 u\w?? ??t 0`o? y t? \ r`h?z 6 ez read ??w??? (r/w bit= ?1?) ? ??`?b{ ak4343 x\w???w ? ?t 0`o? y t? \ r`z| ^?h??w???? z?`z o ?????? 1 m??? ?y??`?b{???u z?^?h?z?u? y t? \ rdc - e? ?qz read ?^x 4 ?`?b{ sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 68. ???????? [ak4343] ms0478-j-02 2010/11 - 67 - scl sda stop condition start condition s p figure 69. ?? eq - e scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 70. i 2 c pw? y t scl sda data line stable; data valid change of data allowed figure 71. i 2 c pw??? 8 [ak4343] ms0478-j-02 2010/11 - 68 - ?? addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pmvcm pmmin pmspk pmlo pmdac 0 0 01h power management 2 0 hpmt n pmhpl pmhpr m/s 0 mcko pmpll 02h signal select 1 sppsn mins dacs dacl 0 0 0 mgain0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 minl 0 0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 06h timer select dvtm wtm2 ztm1 ztm0 wtm1 wtm0 rfst1 rfst0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 09h lch input volume control avl 7 avl6 avl5 avl4 avl 3 avl2 avl1 avl0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 0eh mode control 3 0 0 smut e dvolc bst1 bst0 dem1 dem0 0fh mode control 4 0 0 0 0 avolc hpm minh dach 10h power management 3 inr1 in l1 hpg mdif2 mdif1 inr0 inl0 0 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 20h power management 4 0 0 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl 21h mode control 5 0 0 micr3 micl3 0 0 ain3 rcv 22h lineout mixing select 0 0 0 0 rinr3 linl3 rinr2 linl2 23h hp mixing select 0 0 0 0 rinh3 linh3 rinh2 linh2 24h spk mixing select 0 0 0 0 rins3 lins3 rins2 lins2 note 41. pdn pin ? ?l? tb?qz? ?x s8=^??b{ note 42. ?0? p| ^?h????w ?1? w {v?xe-pb{ [ak4343] ms0478-j-02 2010/11 - 69 - ?i ? addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 0 pm vcm pmmin pmspk pmlo pmdac 0 0 default 0 0 0 0 0 0 0 0 pmdac: dac w??y?? 0: power down (default) 1: power up pmlo: a|??? z?w??y?? 0: power down (default) 1: power up pmspk: e???w??y?? 0: power down (default) 1: power up pmmin: t?? ??w??y?? 0: power down (default) 1: power up 6 \??;x pmmin or pmainl3 bit = ?1? q`o<^m{ pmvcm: vcom w??y?? 0: power down (default) 1: power up ??? ?^^d? ?xz ?c pmvcm bit ? ?1? t`sz?ys??d?{ pmvcm bit t 0 `o ?0? ? {v?\qupv?wxz?? 00h, 01h, 02h, 10h, 20h w ?ow??y ?????q mcko bit ? ?0? tb?izpb{ \w??w???? on/off (?1?/?0?) b?\qp ? $t????b?\qupv?b{?hz pdn pin ? ?l? tb?\qpz?w o0tsxz ?s?? st????b?\qupv? b{\wqv? ?x s8=^??b{ ?hz?? 00h, 01h, 02h, 20h w ?ow??y?????q mcko bit ? ?0? tb?\qpz ? s?? st????b?\qupv?b{\wqv?w o0x-?^?om?b{ dac ??;`sm ?z??????b? ?axk??d?{ dac ??;b? ?x? ????? `o<^m{ [ak4343] ms0478-j-02 2010/11 - 70 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 0 hpmt n pmhpl pmhpr m/s 0 mcko pmpll default 0 0 0 0 0 0 0 0 pmpll: pll w??y?? 0: ext mode and power down (default) 1: pll mode and power up mcko: mcko ??w m? 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. m/s: master / slave mode w ? r 0: slave mode (default) 1: master mode pmhpr: rch ???????w??y?? 0: power down (default) 1: power up pmhpl: lch ???????w??y?? 0: power down (default) 1: power up hpmtn: ???????w??? 0: mute (default) 1: normal operation [ak4343] ms0478-j-02 2010/11 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 sppsn mins dacs dacl 0 0 0 mgain0 default 0 0 0 0 0 0 0 1 mgain1-0: ????????? ( table 22 ) mgain1 bit x 03h w d5 bit pb{ dacl: dac t?a|??? z??hx3???t ??^?? ??w???? 0: off (default) 1: on pmlo bit = ?1? wz\w???x?ts??b{ pmlo bit = ?0? wz lout, rout pins x avss ? z?`?b{ dacs: dac t?e???t ??^?? ??w???? 0: off (default) 1: on ?1? p dac w z? ???e???t ??`?b{ mins: min pin t?e???t ??^?? ??w???? 0: off (default) 1: on ?1? p min pin ?w ?? ???e???t ??`?b{ sppsn: e???w???t?? 0: power save mode (default) 1: normal operation ?0? pe???x???t??ts??b{ \wz spp pin x hi-z z spn pin x hvdd/2 ? z?`?b{ pmspk bit =?1? wz\w???x?ts??b{ [ak4343] ms0478-j-02 2010/11 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 lovl lops mgain1 spkg1 spkg0 minl 0 0 default 0 0 0 0 0 0 0 0 minl: a|??? z? ?hx3???t ??^?? min ??w???? 0: off (default) 1: on pmlo bit = ?1? wz\w???x?ts??b{ pmlo bit = ?0? wz lout, rout pins x avss ? z?`?b{ spkg1-0: e??? z????w ? ( table 53 ) mgain1: ????????? ( table 22 ) lops: a|??? z?w???t?? 0: normal operation (default) 1: power save mode lovl: a|??? / 3? z???? ? ( table 46 , table 47 ) 0: 0db/+6db (default) 1: +2db/+8db addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 default 0 0 0 0 0 0 1 0 dif1-0: |???|????????? ( table 17 ) default: ?10? ( 2g? ) bcko: ?t??w bick z? * t :w ? ( table 11 ) pll3-0: pll , j???w ? r ( table 5 ) default: ?0000?(lrck pin) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 ps1 ps0 fs3 msbs bckp fs2 fs1 fs0 default 0 0 0 0 0 0 0 0 fs3-0: ???? * t : (see table 6 and table 7 ) t| mcki * t :w ? ( table 12 ) pll t??x???? * t :w ? ??mz ext t??x mcki w ?? * t :? ? `? b{ bckp: dsp mode w bick ? q ? ( table 18 ) ?0?: ? ? p sdto z? , ? ? p sdti ??? (default) ?1?: ? ? p sdto z? , ? ? p sdti ??? msbs: dsp mode w lrck ? ? ( table 18 ) ?0?: lrck w ? ? u??? ~ 8w bick r *8 2 (default) ?1?: lrck w ? ? u??? ~ 8w bick 1 *8 2 ps1-0: mcko * t :w ? ( table 10 ) default: ?00?(256fs) [ak4343] ms0478-j-02 2010/11 - 73 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select dvtm wtm2 ztm 1 ztm0 wtm1 wtm0 rfst1 rfst0 default 0 0 0 0 0 0 0 0 rfst1-0: alc ??????w s ( table 30 ) default: ?00? (4 ) { wtm2-0: alc ?? 4;w ? ( table 27 ) alc ?^ t???? ?^u c \`sm ?z?? ?^??o *8? ? `?b{ s8 ?x ?000? (128/fs) pb{ ztm1-0: alc ??????w ? ( table 26 ) ?? {v? ?^z alc ?? ?^t??z???u!?^??wxz??b?t ?hx????`h ?pb{ s8 ?x ?00? (128/fs) pb{ dvtm: digital volume w1?? -?? ? `?b{ 0: 1061/fs (default) 1: 256/fs \w1?? -?x dvl7-0, dvr7-0 bits ? 00h t? ffh ?!?`h ?w -?pb{ addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h alc mode control 1 0 0 alc zelmn lmat1 lmat0 rgain0 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc ????u z ? ?? / ?? 4;??????? ( table 24 ) default: ?00? lmth1 bit x 0bh w d6 bit pb{ rgain1-0: alc ?????a? ( table 28 ) default: ?00? rgain1 bit x 0bh w d7 bit pb{ lmat1-0: alc ???? att a? ( table 25 ) default: ?00? zelmn: alc ???? ?^??u z??? 0: enable (default) 1: disable alc: alc ??? 0: alc disable (default) 1: alc enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h alc mode control 2 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: alc ?? ?^w, j ?w ? { 0.375db step, 242 level ( table 29 ) default: ?e1h? (+30.0db) [ak4343] ms0478-j-02 2010/11 - 74 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lch input volume control avl 7 avl6 avl5 avl4 avl 3 avl2 avl1 avl0 0ch rch input volume control avr7 avr6 avr5 avr4 avr3 avr2 avr1 avr0 default 1 1 1 0 0 0 0 1 avl7-0, avr7-0: alc ???????? ; 0.375db step, 242 level ( table 32 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah lch digital volume control dvl7 dvl6 dvl5 dvl4 dvl3 dvl2 dvl1 dvl0 0dh rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 default 0 0 0 1 1 0 0 0 dvl7-0, dvr7-0: z???????? ( table 35 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 3 rgain1 lmth1 0 0 0 0 vbat 0 default 0 0 0 0 0 0 0 0 vbat: ???????wt? ?y ( table 51 ) 0: 0.5 x hvdd (default) 1: 0.64 x avdd lmth1: alc ????u z ? ?? / ?? 4;??????? ( table 24 ) rgain1: alc ?????a? ( table 28 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh mode control 3 0 loop sm ute dvolc bst1 bst0 dem1 dem0 default 0 0 0 1 0 0 0 1 dem1-0: ?????3???? ( table 33 ) default: ?01? (off) bst1-0: ??4 ys?w???? ( table 34 ) default: ?00? (off) dvolc: ???????w???? 0: independent 1: dependent (default) dvolc bit = ?1? wqvz dvl7-0 bit p????w???????u!=`?b{ ``z dvr7-0 bit t dvl7-0 bit w ?x {v???d?{ smute: 1????????? 0: normal operation (default) 1: dac outputs soft-muted loop: ?? o ????? 0: sdti dac (default) 1: sdto dac [ak4343] ms0478-j-02 2010/11 - 75 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh mode control 4 0 0 0 0 avolc hpm minh dach default 0 0 0 0 1 0 0 0 dach: dac t????????t ??^?? ??w???? 0: off (default) 1: on minh: min pin t????????t ??^?? ??w???? 0: off (default) 1: on hpm: ?????wt?? z? 0: a| (default) 1: t?? hpm bit = ?1? wqvz dac w z? ??x (l+r)/2 q`o???????t? z?^??b{ avolc: avol w???? 0: independent 1: dependent (default) avolc bit = ?1? wqvz avl7-0 bit p????w avol u!=`?b{ ``z avr7-0 bit t avl7-0 bit w ?x {v???d?{ addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 3 inr1 in l1 hpg mdif2 mdif1 inr0 inl0 0 default 0 0 0 0 0 0 0 0 inl1-0: gain-amp lch ??1? ? r ( table 22 ) default: 00 (lin1 pin) inr1-0: gain-amp rch ??1? ? r ( table 22 ) default: 00 (rin1 pin) mdif1: 3????? / ) ? ?? ~ 8 1 0: 3????? ?? (lin1/rin1 pin: default) 1: ) ? ?? (in1+/in1 ? pin) \w???x pin#32 q #31 w ??? ? `?b{ mdif2: 3????? / ) ? ?? ~ 8 2 0: 3????? ?? (lin2/rin2 pin: default) 1: ) ? ?? (in2+/in2 ? pin) \w???x pin#30 q #29 w ??? ? `?b{ hpg: ?????????? ? ( table 49 ) 0: 0db (default) 1: +3.6db [ak4343] ms0478-j-02 2010/11 - 76 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h digital filter select gn1 gn0 0 fil1 eq fil3 0 0 default 0 0 0 0 0 0 0 0 gn1-0: gain ?w??? ? ( table 23 ) default: ?00? (0db) fil3: a| e; fil3 w : ? ? 0: ? (default) 1: ? fil3 bit = ?1? wqvz f3a13-0, f3b13-0 bit w ? u?ts??b{ fil3 bit = ?0? wqvz fil3 ??x off(mute) pb{ eq: ???4 y;????w : ? ? 0: ? (default) 1: ? eq bit = ?1? wqvz eqa15-0, eqb13-0, eqc15-0 bit w ? u?ts??b{ eq bit = ?0? wqvz eq ??x?? (0db) pb{ fil1: ~?;????; fil1 w : ? ? 0: ? (default) 1: ? fil1 bit = ?1? wqvz f1a13-0, f1b13-0 bit w ? u?ts??b{ fil1 bit = ?0? wqvz fil1 ??x?? (0db) pb{ [ak4343] ms0478-j-02 2010/11 - 77 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 13h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 14h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 15h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 16h eq co-efficient 0 eqa7 eqa6 e qa5 eqa4 eqa3 eqa2 eqa1 eqa0 17h eq co-efficient 1 eqa15 eqa1 4 eqa13 eqa12 eqa11 eqa10 eqa9 eqa8 18h eq co-efficient 2 eqb7 eqb6 eq b5 eqb4 eqb3 eqb2 eqb1 eqb0 19h eq co-efficient 3 0 0 eqb13 eqb12 eqb11 eqb10 eqb9 eqb8 1ah eq co-efficient 4 eqc7 eqc6 eq c5 eqc4 eqc3 eqc2 eqc1 eqc0 1bh eq co-efficient 5 eqc15 eqc14 e qc13 eqc12 eqc11 eqc10 eqc9 eqc8 1ch fil1 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1dh fil1 co-efficient 1 f1as 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 1eh fil1 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 1fh fil1 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: a| e; fil3 : (14bit x 2) default: ?0000h? f3as: a| e; fil3 w ? r 0: hpf (default) 1: lpf eqa15-0, eqb13-0, eqc15-c0: ???4 y;???? : (14bit x 2 + 16bit x 1) default: ?0000h? f1a13-0, f1b13-b0: ~?;????; fil1 : (14bit x 2) default: ?0000h? f1as: ~?;????; fil1 w ? r 0: hpf (default) 1: lpf [ak4343] ms0478-j-02 2010/11 - 78 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 20h power management 4 0 0 pmainr3 pmainl3 pmainr2 pmainl2 pmmicr pmmicl default 0 0 0 0 0 0 0 0 pmmicl: gain-amp lch w??y?? 0: power down (default) 1: power up pmmicr: gain-amp rch w??y?? 0: power down (default) 1: power up pmainl2: lin2 ??3??s?w??y?? 0: power down (default) 1: power up pmainr2: rin2 ??3??s?w??y?? 0: power down (default) 1: power up pmainl3: lin3 ??3??s?w??y?? 0: power down (default) 1: power up 6 \??;x pmmin or pmainl3 bit = ?1? q`o<^m{ pmainr3: rin3 ??3??s?w??y?? 0: power down (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 21h mode control 5 0 0 micr3 micl3 0 0 ain3 rcv default 0 0 0 0 0 0 0 0 rcv: receiver select 0: stereo line output (lout/rout pins) (defautl) 1: mono receiver out put (rcp/rcn pins) ain3: analog mixing select 0: mono input (min pin) (default) 1: stereo input (lin3/rin3 pins): pll is not available. micl3: ??3?? ? 0: lin3 pin ?? (default) 1: gain-amp lch z? micr3: ??3?? ? 0: rin3 pin ?? (default) 1: gain-amp rch z? [ak4343] ms0478-j-02 2010/11 - 79 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h lineout mixing select 0 0 0 0 rinr3 linl3 rinr2 linl2 default 0 0 0 0 0 0 0 0 linl2: lin2 t?a|??? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on rinr2: rin2 t?a|??? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on linl3: lin3 (or gain-amp lch) t?a|??? z?t ??^?? ??w???? 0: off (default) 1: on rinr3: rin3 (or gain-amp rch) t?a|??? z?t ??^?? ??w???? 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 23h hp mixing select 0 0 0 0 rinh3 linh3 rinh2 linh2 default 0 0 0 0 0 0 0 0 linh2: lin2 t?????? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on rinh2: rin2 t?????? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on linh3: lin3 (or gain-amp lch) t?????? z?t ??^?? ??w???? 0: off (default) 1: on rinh3: rin3 (or gain-amp rch) t?????? z?t ??^?? ??w???? 0: off (default) 1: on [ak4343] ms0478-j-02 2010/11 - 80 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 24h spk mixing select 0 0 0 0 rins3 lins3 rins2 lins2 default 0 0 0 0 0 0 0 0 lins2: lin2 t?e? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on rins2: rin2 t?e? z?t ??^?? ??w???? (gain-amp ? ) 0: off (default) 1: on lins3: lin3 (or gain-amp lch) t?e? z?t ??^?? ??w???? 0: off (default) 1: on rins3: rin3 (or gain-amp rch) t?e? z?t ??^?? ??w???? 0: off (default) 1: on [ak4343] ms0478-j-02 2010/11 - 81 - 3a ?- figure 72 s?| figure 73 x3a ? ?pb{ . $ss?q ?tmmox a??? (akd4343) ? ? `o<^m{ mutet rou t lout min rin2 lin2 lin1 rin1 hpl hpr hvss hvdd spp spn mcko mcki test1 vcom a vss a vdd vcoc i2c pdn csn dvss dvdd bick lrck test2 sdti cdti cclk a k4343 top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 line in 1u 0.1u 2.2u 0.1u rp 6.8 47u 6.8 47u 10 0.22u 10 0.22u power supply 2.6 3.6v 0.1u 0.1u 10 dsp p line out headphone speaker mono in cp 10u analog ground digital ground 1u 1u 200 200 20 k 20 k zd2 zd1 dynamic spk r1, r2: sho rt zd1, zd2: open piezo spk r1, r2: 10 zd1, zd2: required r1 r 2 ? : - ak4343 w avss, dvss, hvss q *%???? sw????x zo `o<^m{ - ???? ??e?x|??t`smp<^m{ - ext t?? (pmpll bit = ?0?) w ?z vcoc pin x|??p?m?d?{ - pll t?? (pmpll bit = ?1?) w ?z cp q rp x table 5 w?ot`o<^m{ - y ?e??;x hvdd t 2.6 5.25v w ?o???`z spp, spn pin tf?g? 10 ? w3 ??? ?? ? `o<^m{ - ?t??p?;b? ?z m/s bit t ?1? u {v????pz ak4343 w lrck, bick pin x? ?a???w y 6pb{fwh?z ak4343 w lrck, bick pin t 100k sw???k? mx??? ?? ??? ?auk??b{ figure 72. 3a ? $ (ain3 bit = ?0?, rcv bit = ?0?) [ak4343] ms0478-j-02 2010/11 - 82 - mutet rcn rcp lin3 rin2 lin2 lin1 rin1 hpl hpr hvss hvdd spp spn mcko mcki test1 vcom a vss a vdd rin3 i2c pdn csn dvss dvdd bick lrck test2 sdti cdti cclk a k4343 top view 25 26 27 28 29 30 31 32 24 23 22 1 16 15 14 13 12 11 10 9 21 20 19 18 17 2 3 4 5 6 7 8 line in 1u 0.1u 2.2u 0.1u 6.8 47u 6.8 47u 10 0.22u 10 0.22u power supply 2.6 3.6v 0.1u 0.1u 10 dsp p receiver headphone speaker 10u analog ground digital ground zd2 zd1 dynamic spk r1, r2: sho rt zd1, zd2: open piezo spk r1, r2: 10 zd1, zd2: required r1 r 2 ? : - ak4343 w avss, dvss, hvss q *%???? sw????x zo `o<^m{ - ???? ??e?x|??t`smp<^m{ - ain3 bit = ?1? w ?z pll x?;pv?d?{ - y ?e??;x hvdd t 2.6 5.25v w ?o???`z spp, spn pin tf?g? 10 ? w3 ??? ?? ? `o<^m{ figure 73. 3a ? $ (ain3 bit = ?1?, rcv bit = ?1?, pll ?; ?d , ??? ?? ) [ak4343] ms0478-j-02 2010/11 - 83 - 1. ????q ?ow????? ?oq????w ?mtx g ??`o<^m{ z avdd, dvdd, hvdd tx3aw??? ? o???`?b{ avdd, dvdd, hvdd u ?op??^?? ?txz ?oqj [3?-???q? ?axk??d?{ avss, dvss, hvss x???????t ? `o<^m{3aw????x?? ?q????p zo ` pc ??? w ?otmq\?p ? `o<^m{ ?0?w???? ????xs??x ?oe?wxt ? `o<^m{ 2. , j ?y vcom x??? ??wt? ?yq`o????b{\we?tx? * t??? ??b?h?t 2.2 f sw ?r???q?t 0.1 f w???????? avss qwt ? `o<^m{ ?tz? ??????xe?tpv?iznzo ? `o<^m{ vcom pin t? ?v? loxmz?d?{ ???? ??z ?t???x! e+?w????? ?z?h?z vcom pin t?pv?izm`o <^m{ 3. ??? ?? ?? ??z??? ??q min ??x3????? ??tslom?b{?? ??q??? ??w ?? ?x o ?wt? ?y (0.45 x avdd) ? t 0.06 x avdd vpp(typ)@mgain1-0 bits = ?01?, 0.03 x avdd vpp(typ)@mgain1-0 bits = ?10?, 0.015 x avdd vpp(typ)@mgain1-0 bits = ?11? ?hxz 0.6 x avdd vpp(typ)@mgain1-0 bits = ?00? ts??b{ min ??w ???x o ?wt? ?y (0.45 x avdd) ? t 0.6 x avdd vpp(typ) ts??b{ z ?? ??x???p dc ??`?b{\w??|? * t :x fc=1/(2 rc) pb{ ak4343 x avss t? avdd ?pw ?y? ??b?\qupv?b{ 4. ??? z? dac t 0b? ?????w????x 2?s ??y??pz 7fffh(@16bit) t 0`ox yw??-? ?z 8000h(@16bit) t 0`ox ?w??-??z 0000h(@16bit) pwg? ?x vcom ?ypb{ vcom ?y xza|??? z?q3? z?px 0.45 x avdd (typ) ? t z?^?z????? z?qe ? z?px hvdd/2 ? t z?^??b{ [ak4343] ms0478-j-02 2010/11 - 84 - ????3?-? ???w ? dac ? power-up tx???u??^?om? ?auk??b{ 1. pll ?t??w ? bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) mcko pin output (8) (7) 40msec(max) example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:01h, data:08h addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:0bh mcko, bick and lrck output figure 74. clock set up sequence (1) < q? > (1) ?oqj [?z pdn pin ?l? ? ?h? \wx ak4343 w???wh?z 150ns ? w ?l? u ?apb{ (2) \wtz dif1-0, pll3-0, fs3-0, bcko, m/s bits w ? ??lo<^m{ (3) vcom w???? : pmvcm bit = ?0? ? ?1? ???qj [? 2t7 st vcom ?qj [o<^m{ (4) mcko z???;b? ? : mcko bit = ?1? mcko z???;`sm ? : mcko bit = ?0? (5) pmpll bit u ?0? ? ?1? ts?z mcki pin t???u??^?h?z pll ?^u???`?b{ pll w??x 40ms(max) pb{ (6) pll u? ?z bick, lrck ? z?`??z y s ?^u??`?b{ (7) mcko bit = ?1? w ?z\wpx mcko pin t? y psm???u z?^??b{ (8) mcko bit = ?1? w ?z pll u? ? mcko pin t? y s???u z?^??b{ [ak4343] ms0478-j-02 2010/11 - 85 - 2. pll ?t??p? ???? (lrck or bick pin) ??;b? ? pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) (5) input 4fs of example: audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:32h addr:05h, data:27h (4) addr:01h, data:01h figure 75. clock set up sequence (2) < q? > (1) ?oqj [?z pdn pin ?l? ? ?h? \wx ak4343 w???wh?z 150ns ? w ?l? u ?apb{ (2) \wtz dif1-0, fs3-0, pll3-0 bits w ? ??lo<^m{ (3) vcom w???? : pmvcm bit = ?0? ? ?1? ???qj [? 2t7 st vcom ?qj [o<^m{ (4) pmpll bit u ?0? ? ?1? ts?z pll , j??? (lrck or bick pin) u??^?h?z pll ?^u ???`?b{ pll w??x lrck u pll , j??? ??w ?z 160ms(max), bick u pll , j???w ?z 2ms(max) pb{ (5) pll u? ?z y s ?^u??`?b{ [ak4343] ms0478-j-02 2010/11 - 86 - 3. pll ?t??p? ???? (mcki pin) ??;b? ? bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: msb justified input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:00h, data:40h (2)addr:04h, data:4ah addr:05h, data:27h (4)addr:01h, data:03h mcko output start bick and lrck input start figure 76. clock set up sequence (3) < q? > (1) ?oqj [?z pdn pin ?l? ? ?h? \wx ak4343 w???wh?z 150ns ? w ?l? u ?apb{ (2) \wtz dif1-0, pll3-0, fs3-0 bits w ? ??lo<^m{ (3) vcom w???? pmvcm bit = ?0? ? ?1? ???qj [? 2t7 st vcom ?qj [o<^m{ (4) mcko z?w ? : mcko bit = ?1? (5) pmpll bit u ?0? ? ?1? ts?z mcki pin t???u??^?h?z pll ?^u???`?b{ pll w??x 40ms(max) pb{ (6) pll u? ?z mcko pin t? y s???u z?^??b{ (7) \wpxz mcko pin t? y psm???u z?^??b{ (8) mcko ???t ?8`h bick, lrck ???? ??`oxi^m{ [ak4343] ms0478-j-02 2010/11 - 87 - 4. ? ????t??p?;b? ? ( ?t?? ) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format: msb justified input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:00h, data:40h (2) addr:04h, data:02h addr:05h, data:00h mcki, bick and lrck input figure 77. clock set up sequence (4) < q? > (1) ?oqj [?z pdn pin ?l? ? ?h? \wx ak4343 w???wh?z 150ns ? w ?l? u ?apb{ (2) \wtz dif1-0, fs1-0 bits w ? ??lo<^m{ (3) vcom w???? pmvcm bit = ?0? ? ?1? ???qj [? 2t7 st vcom ?qj [o<^m{ (4) mcki, lrck, bick ??? ???z y s ?^u??`?b{ [ak4343] ms0478-j-02 2010/11 - 88 - 5. ? ????t??p?;b? ? ( ?t?? ) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (3) (4) lrck pin bick pin (2) mcki pin input m/s bit (addr:01h, d3) output example: audio i/f format: msb justified input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (4) addr:00h, data:40h (3) addr:04h, data:02h addr:05h, data:00h addr:01h, data:08h bick and lrck output (2) mcki input figure 78. clock set up sequence (5) < q? > (1) ?oqj [?z pdn pin ?l? ? ?h? \wx ak4343 w???wh?z 150ns ? w ?l? u ?apb{ (2) mcki ? ??`o<^m{ (3) dif1-0, fs1-0 bits w ? ?z m/s bit ? ?1? t ? `o<^m{ lrck s?| bick u z?^??b{ (4) vcom w???? pmvcm bit = ?0? ? ?1? ???qj [? 2t7 st vcom ?qj [o<^m{ [ak4343] ms0478-j-02 2010/11 - 89 - e? z? fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmspk bit (addr:00h, d4) 1,111 0,000 18h 28h spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (1) (9) 1 0 (7) alc bit (addr:07h, d5) (10) (11) (14) (12) dacs bit (addr:02h, d5) (13) 01 00 (3) spkg1-0 bits (addr:03h, d4-3) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (8) (2) (6) alc control 1 (addr:06h) 00h 3ch (4) alc control 2 (addr:08h) e1h c1h (5) alc control 3 (addr:0bh) 00h 00h pmmin bit (addr:00h, d5) example: pll master mode audio i/f format: msb justified sampling frequency: 44.1khz digital volume: -8db alc: enable (2) addr:02h, data:20h (7) addr:07h, data:20h (1) addr:05h, data:27h (9) addr:0ah & 0dh, data:28h (10) addr:00h, data:74h (11) addr:02h, data:a0h (12) addr:02h, data:20h playback (13) addr:02h, data:00h (14) addr:00h, data:40h (3) addr:03h, data:08h (8) addr:09h & 0ch, data:91h (4) addr:06h, data:3ch (5) addr:08h, data:e1h (6) addr:0bh, data:00h figure 79. speaker-amp output sequence < q? > ????w ? w?? `z??????`o<^m{ (1) ???? * t : (fs3-0 bits) ? ? `o<^m{ pll t??w ?z???? * t :?!?` ot?w pll ?????`z (5) w dac t|e?w??????lo<^m{ (2) dac ? spk-amp ww ? : dacs bit = ?0? ? ?1? (3) spk-amp ??? ? : spkg1-0 bits = ?00? ?01? (4) alc timer ( ?? 06h) w ? (5) alc ref ? ( ?? 08h) w ? (6) lmth1, rgain1 bits w ? ( ?? 0bh) (7) lmth0, rgain0, lmat1-0, alc bits w ? ( ?? 07h) (8) alc ???????? ( ?? 09h&0ch) w ? avl7-0 = avr7-0 bits = ?91h?(0db) t ? `o<^m{ (9) z???????? ( ?? 0ah&0dh) w ? { dvolc bit = ?1?(default) wqvz dvl7-0bits(0ah) p lch s?| rch w?mw???? ? `? b{ dac u????^?h?z default ? (0db) t? ? `h ?t1?? -?`omv?b{ (10) dac, min-amp t|e?w???? : pmdac = pmmin = pmspk bits = ?0? ?1? s8=??? (1059/fs=24ms@fs=44.1khz) z dac ?????x o ?p 2?s ??y??w ?0? t { ^??b{ s8=???u 4?b?qz dac w ? (25/fs=0.5ms@fs=44.1khz) &a?z dac z?x???? ?? ??t pb? ?yts??b{ alc bit = ?1? w ?z s8=??? (1059/fs = 24ms @fs=44.1khz) z alc x???? y 6 (alc w???x avl/r7-0 bits w ? ) pz s8=???u 4?b?q alc x avl/r7-0 bits w ? t? ?^???`?b{ (11) e?w???t??wr ? : sppsn bit = ?0? ?1? (12) e?w???t????? : sppsn bit = ?1? ?0? (13) dac ? spk-amp ww disable: dacs bit = ?1? ? ?0? (14) dac, min-amp t|e?w???? : pmdac = pmmin = pmspk bits = ?1? ?0? [ak4343] ms0478-j-02 2010/11 - 90 - e?t?w mono ?? z? dacs bit (addr:02h, d5) pmspk bit (addr:00h, d4) mins bit (addr:02h, d6) spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (2) (1) (5) (4) pmmin bit (addr:00h, d5) 1 0 clocks can be stopped. clock (3) (6) example: (2) addr:02h, data:60h (1) addr:00h, data:70h (3) addr:02h, data:e0h mono signal output (4) addr:02h, data:60h (5) addr:00h, data:40h (6) addr:02h, data:00h figure 80. ?min-amp ? speaker-amp? output sequence < q? > ?min-amp ? spk-amp? w?w ?^pxz???x??^?om? ?axk??d?{ (1) min-amp t|e?w???? : pmmin = pmspk bits = ?0? ?1? (2) dac ? spk-amp ww disable: dacs bit = ?0? min ? spk-amp ww enable: mins bit = ?0? ?1? (3) e?w???t??wr ? : sppsn bit = ?0? ?1? (4) e?w???t????? : sppsn bit = ?1? ?0? (5) min-amp t|e?w???? : pmmin = pmspk bits = ?1? ?0? (6) min ? spk-amp ww disable: mins bit = ?1? ?0? [ak4343] ms0478-j-02 2010/11 - 91 - ????? z? fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmhpl/r bits (addr:01h, d5-4) hpmtn bit (addr:01h, d6) hpl/r pins 1,111 0,000 18h 28h normal output (1) bst1-0 bits (addr:0eh, d3-2) 00 10 00 (3) (5) (12) pmdac bit (addr:00h, d2) (6) (11) (7) (9) (8) (10) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (4) pmmin bit (addr:00h, d5) dach bit (addr:0fh, d0) (2) (13) example: pll, master mode audio i/f format :msb justified (adc & dac) sampling frequency: 44.1khz digital volume: ? 8db bass boost level : midddle (1) addr:05h, data:27h (2) addr:0fh, data:09h (4) addr:09h&0ch, data:91h (5) addr:0ah&0dh, data:28h (6) addr:00h, data:64h (7) addr:01h, data:39h (8) addr:01h, data:79h playback (9) addr:01h, data:39h (10) addr:01h, data:09h (11) addr:00h, data:40h (3) addr:0eh, data:19h (12) addr:0eh, data:11h (13) addr:0fh, data:08h figure 81. headphone-amp output sequence < q? > ????w ? w?? `z??????`o<^m{ (1) ???? * t : (fs3-0 bits) ? ? `o<^m{ pll t??w ?z???? * t :?!?` ot?w pll ?????`z (5) w dac t|e?w??????lo<^m{ (2) dac ? hp-amp w ? : dach bit = ?0? ?1? (3) ???? (bst1-0 bits) w ? { (4) alc ???????? ( ?? 09h&0ch) w ? avl7-0 = avr7-0 bits = ?91h?(0db) t ? `o<^m{ (5) z???????? ( ?? 0ah&0dh) w ? { dvolc bit = ?1?(default) wqvz dvl7-0bits(0ah) p lch s?| rch w?mw???? ? `? b{ dac u????^?h?z default ? (0db) t? ? `h ?t1?? -?`omv?b{ (6) dac s?| min-amp w???? : pmdac = pmmin bits = ?0? ?1? s8=??? (1059/fs=24ms@fs=44.1khz) z dac ?????x o ?p 2?s ??y??w ?0? t { ^??b{ s8=???u 4?b?qz dac w ? (25/fs=0.5ms@fs=44.1khz) &a?z dac z?x???? ?? ??t pb? ?yts??b{ alc bit = ?1? w ?z s8=??? (1059/fs = 24ms @fs=44.1khz) z alc x???? y 6 (alc w???x avl/r7-0 bits w ? ) pz s8=???u 4?b?q alc x avl/r7-0 bits w ? t? ?^???`?b{ (7) ???????w???? : pmhpl = pmhpr bits = ?0? ?1? z?x hvss w??pb{ (8) ???????wt? ?yqj [ : hpmtn bit = ?0? ?1? qj [x mutet pin w???w0?q hvdd p>???b{ mutet pin w??? c = 1 f, hvdd=3.3v ww :x r =100ms(typ), 250ms(max) pb{ (9) ???????wt? ?yqj<[ : hpmtn bit = ?1? ?0? qj [x mutet pin w???w0?q hvdd p>???b{ mutet pin w??? c = 1 f, hvdd=3.3v ww :x f =100ms(typ), 250ms(max) pb{ t? ?yu hvss ?<u? 2t ?o?|?b?tz?hxz???????????? `h ?z?;u c \`?b{t? ?yu hvss ?<u??pwx :w 2 w pb{ (10) ???????w???? : pmhpl = pmhpr bits = ?1? ?0? (11) dac s?| min-amp w???? : pmdac = pmmin bits = ?1? ?0? (12) ??w off: bst1-0 bits = ?00? (13) dac ? hp-amp ww disable: dach bit = ?1? ?0? [ak4343] ms0478-j-02 2010/11 - 92 - a|??? z? fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmlo bit (addr:00h, d3) 1,111 0,000 18h 28h lout pin rout pin (1) (4) (5) (2) dacl bit (addr:02h, d4) (10) normal output (7) lops bit (addr:03h, d6) (6) >300 ms (8) (9) >300 ms (11) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (3) pmmin bit (addr:00h, d5) example: pll, master mode audio i/f format :msb justified (adc & dac) sampling frequency: 44.1khz digital volume: ? 8db lovl=minl bits = ?0? (1) addr:05h, data:27h (2) addr:02h, data:10h (4) addr:0ah&0dh, data:28h (5) addr:03h, data:40h (6) addr:00h, data:6ch (7) addr:03h, data:00h playback (8) addr:03h, data:40h (9) addr:00h, data:40h (10) addr:02h, data:00h (11) addr:03h, data:00h (3) addr:09h&0ch, data:91h figure 82. stereo lineout sequence < q? > ????w ? w?? `z??????`o<^m{ (1) ???? * t : (fs3-0 bits) ? ? `o<^m{ pll t??w ?z???? * t :?!? `ot?w pll ?????`z (5) w dac t|e?w??????lo<^m{ (2) dac ? a|??? z?ww ? : dacl bit = ?0? ? ?1? (3) alc ???????? ( ?? 09h&0ch) w ? avl7-0 = avr7-0 bits = ?91h?(0db) t ? `o<^m{ (4) z???????? ( ?? 0ah&0dh) w ? { dvolc bit = ?1?(default) wqvz dvl7-0bits(0ah) p lch s?| rch w?mw???? ? `? b{ dac u????^?h?z default ? (0db) t? ? `h ?t1?? -?`omv?b{ (5) a|??? z?????t????? : lops bit = ?0? ? ?1? (6) dac, min-amp t|a|??? z?w???? : pmdac = pmmin = pmlo bits = ?0? ?1? s8=??? (1059/fs=24ms@fs=44.1khz) z dac ?????x o ?p 2?s ??y??w ?0? t{ ^??b{ s8=???u 4?b?qz dac w ? (25/fs=0.5ms@fs=44.1khz) &a?z dac z?x???? ?? ??t pb? ?yts??b{ alc bit = ?1? w ?z s8=??? (1059/fs = 24ms @fs=44.1khz) z alc x???? y 6 (alc w???x avl/r7-0 bits w ? ) pz s8=???u 4?b?q alc x avl/r7-0 bits w ? t? ?^???`?b{ pmlo bit = ?1? p lout, rout pins uqj u????b{qj u?x c = 1 f, avdd=3.3v wqv max. 300ms pb{ (7) a|??? z?w???t??wr ? : lops bit = ?1? ? ?0? lout, rout pins uqj ulh?z ? ??loxi^m{ ? ?z lout, rout pins t?w; ` z?u??^??b{ (8) a|??? z?????t????? : lops bit: ?0? ? ?1? (9) dac, min-amp t|a|??? z?w???? : pmdac = pmmin = pmlo bits = ?1? ?0? lout, rout pins uqj<u????b{qj<u?x c = 1 f, avdd=3.3v wqv max. 300ms pb{ (10) dac ? a|??? z?ww disable: dacl bit = ?1? ? ?0? (11) a|??? z?w???t??wr ? : lops bit = ?1? ? ?0? lout, rout pins uqj<ulh?z ? ??loxi^m{ [ak4343] ms0478-j-02 2010/11 - 93 - 3? z? fs3-0 bits (addr:05h, d5&d2-0) dvl/r7-0 bits (addr:0ah&0dh, d7-0) pmdac bit (addr:00h, d2) pmlo bit (addr:00h, d3) 1,111 0,000 18h 28h rcp pin normal output lops bit (addr:03h, d6) hi-z hi-z rcn pin normal output hi-z hi-z vcom vcom (1) (6) (7) (8) (11) (9) dacl bit (addr:02h, d4) (10) ivl/r7-0 bits (addr:09h&0ch, d7-0) e1h 91h (5) (3) pmmin bit (addr:00h, d5) rcv bit (addr:21h, d0) (2) (4) example: pll master mode audio i/f format: msb justified (adc & dac) sampling frequency: 44.1khz digital volume: ? 8db lovl = minl bits = ?0? (3) addr:02h, data:10h (1) addr:05h, data:27h (6) addr:0ah & 0dh, data:28h (7) addr:00h, data:6ch (8) addr:03h, data:00h (9) addr:03h, data:40h playback (10) addr:02h, data:00h (11) addr:00h, data:40h (5) addr:09h & 0ch, data:91h (2) addr:21h, data:01h (4) addr:03h, data:40h figure 83. receiver-amp output sequence < q? > ????w ? w?? `z??????`o<^m{ (1) ???? * t : (fs3-0 bits) ? ? `o<^m{ pll t??w ?z???? * t :?!? `ot?w pll ?????`z (5) w dac t|3?w??????lo<^m{ (2) dac ? rcv-amp ww ? s?|???t?? ? : dacl=lops bit = ?0? ? ?1? (3) rcv-amp ? : rcv bit = ?1? (4) dac ? rcv-amp ww ? : dacl bit = ?0? ? ?1? (5) ???t?? ? : lops bit = ?0? ? ?1? (6) alc ???????? ( ?? 09h&0ch) w ? avl7-0 = avr7-0 bits = ?91h?(0db) t ? `o<^m{ (7) z???????? ( ?? 0ah&0dh) w ? { dvolc bit = ?1?(default) wqvz dvl7-0bits(0ah) p lch s?| rch w?mw???? ? `? b{ dac u????^?h?z default ? (0db) t? ? `h ?t1?? -?`omv?b{ (8) dac, min-amp t|3?w???? : pmdac = pmmin = pmlo bits = ?0? ?1? s8=??? (1059/fs=24ms@fs=44.1khz) z dac ?????x o ?p 2?s ??y??w ?0? t { ^??b{ s8=???u 4?b?qz dac w ? (25/fs=0.5ms@fs=44.1khz) &a?z dac z?x???? ?? ??t pb? ?yts??b{ (9) 3?w???t??wr ? : lops bit = ?1? ?0? (10) 3?w???t????? : lops bit = ?0? ?1? (11) dac ? rcv-amp ww disable: dacl bit = ?1? ? ?0? (12) dac, min-amp t|3?w???? : pmdac = pmmin = pmlo bits = ?1? ?0? [ak4343] ms0478-j-02 2010/11 - 94 - ???w - dac ??;`sm ?xz????? -b?\qupv?b{ 1. pll ?t??w ? external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "1" or "0" example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz (3) stop an external mcki (1) (2) addr:01h, data:08h figure 84. clock stopping sequence (1) < q? > (1) pll w???? : pmpll bit = ?1? ?0? (2) mcko z?w - : mcko bit = ?1? ?0? (3) ? ?????-?o<^m{ 2. pll ?t?? (lrck, bick pin) w ? external bick pmpll bit (addr:01h, d0) input (1) (2) external lrck input (2) example audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 85. clock stopping sequence (2) < q? > (1) pll w???? : pmpll bit = ?1? ?0? (2) ? ?????-?o<^m{ 3. pll ?t?? (mcki pin) w ? external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified pll reference clock: mcki bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 86. clock stopping sequence (3) < q? > (1) pll w???? : pmpll bit = ?1? ?0? mcko z?w - : mcko bit = ?1? ?0? (2) ? ?????-?o<^m{ [ak4343] ms0478-j-02 2010/11 - 95 - 4. ? ?????t??w ? external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified input mcki frequency:1024fs (1) stop the external clocks figure 87. clock stopping sequence (4) < q? > (1) ? ?????-?o<^m{ 5. ? ?????t??w ? lrck output bick output external mcki input (1) "h" or "l" "h" or "l" example audio i/f format :msb justified input mcki frequency:1024fs (1) stop the external mcki figure 88. clock stopping sequence (5) < q? > (1) mcki ?-?o<^m{ bick s?| lrck x ?h? ?hx ?l? t{ ^??b{ ???? ???????`z ??? -tm pmvcm bit = ?0? qb?\qp ?v?3????? (typ. 10 a) pv?b{?hz??? -tm pdn pin = ?l? qb?\qp ?v?3????? (typ. 10 a) b ?\q?d pb{ ``z\w ??u s8=^??b [ak4343] ms0478-j-02 2010/11 - 96 - ?-? 32pin qfn (unit: mm) 4.75 0.10 5.00 0.10 4.75 0.10 0.50 0.23 24 17 25 1 16 1 0.01 0.08 32 8 9 c0.42 32 +0.07 -0.05 0.40 0.10 0.20 + 0.04 - 0.01 c exposed pad 3.5 5.00 0.10 0.85 0.05 c b a 0.10 m ab 3.5 ? : ?-?j? we z?? (exposed pad) xz|???hx????t ? `o<^m ( note 7 ? ) { p~y???7 ?-?p : ?3% % ?????p : ? ????? rg : r >y?? [ak4343] ms0478-j-02 2010/11 - 97 - ???? (ak4343en) a k4343 x xxxx 1 a km xxxxx : date code identifier (5 ; ) ???? (AK4343VN) 4343vn x xxx x 1 a km xxxxx : date code identifier (5 ; ) [ak4343] ms0478-j-02 2010/11 - 98 - ~ do date revision reason page contents 06/04/04 00 s [ ?7!? 35-36 ???? ?) ? ??p?;b? ?z table 20 p ?x? 1wmm om?e?tx ??? ??`smpxi^m{ ? c{ table 20(handling of line input pins) ?c{ 06/10/24 01 ?g y 53 a|??? z?????3?-? ???? ? : pmlo bit = ?1? ? pmlo bit = ?0? 65 i 2 c ????t?? ? ? 3 ???x ?0? { pb ? ? ? 2 ???x ?0? { pb 75 ? ?i ? (addr=0fh) hpm bit: ? hpm bit = ?1? wqvz (l+r)/2 w ??u? ??????t? z?^??b{ hpm bit = ?1? wqvz pmhpl = pmhpr bits = ?1? p?;`o<^ m{ ? ? hpm bit = ?1? wqvz dac w z? ??x (l+r)/2 q`o???????t? z?^??b{ 87 ????3?-? (clock setup: ext slave mode) mclk frequency: 1024fs ? 256fs addr=05h: data=27h ? 00h 88 ????3?-? (clock setup: ext master mode) mclk frequency: 1024fs ? 256fs addr=05h: data=27h ? 00h 06/10/24 01 ?g y 91 ????3?-? (headphone playback) digital volume level: 0db ? ? 8db addr=0eh: data=14h ? 19h figure 81: (12) addr=0eh: data=00h ? 11h 94 ????3?-? (clock stop: pll master mode) mcko bit = ?h? or ?l? ? ?1? or ?0? 10/12/02 02 g \ ?c AK4343VN wg \? ?c [ak4343] ms0478-j-02 2010/11 - 99 - oas ??? z ? {tgl^?h a ?zs?|z a ?w?7tmv?`oxz a ?~ 3wh?t'sx!?b?\quk?? b{ hm?`oz]?;?u |wmtxz? {t l`h ?cu7 yw?wpk?\q?t? r pzk?m xt ?? 3? r pt]? yxi^m{ z ? {tgl^?h *%s?z ;s?z1???s?|\??tb? ?cxz r ? . a ?w ?^?z ;?? ?b??wpb{sl7w;+ ?-tsmo? {tgl^?h *%s?z ;s?z1???s? |\??tb? ?c??;^?? ?xzsl7w y tsmo?loxi^m{? {tgl^?h *% s?z ;s?z1???s?|\??tb? ?cw?;ti?`osl7?hx h~ t \ah ? t 0`ztxfw y ? ?o?wpxk??d?{?hz p??;ti?b?z? tvfw w h~ w tb?vbt 0b? ??tmv?`o? ?7pb{ z ? {gl a ?uz?? 8s?|z?u?got ?? ?t ?t???t? pb? ?z zb ?mt ?ot,nx z?du ?apb{ z ??;+z? ? ?z? |;;+zj? ? m?;;+srzfw ?~;+w? ?? ?^ ??uz ?? hx ??e?cz \?z .zr? s? o gs ??t?b\qu ' y^???os??o?m ?t q ?a{^??; mtt a ???;^?? ?x z ?c? 2tt e tw {?t?? ???s ?xi ^m{ z \w ?? {? ?ct\o`h; mtt a ???;^?h ?ztxzfw?;t? \c? ? sw y ? ~ ?o?wpxk??d?wp]? ?xi^m{ z sl7w 8 st??\w ???w o? ??ct g; mtt a ?u?;^?zfw?;t? ? s u \ah ?x ?osl7to] ? r?hx4 ?`o ?v?bwp]? ?<^m{ |
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